semi合集-English.pdf - 第5281页

SEMI M47-0704 © SEMI 2001, 2004 1 SEMI M47-0704 SPECIFICATION FOR SILI CON-ON-I NSULATOR (SOI) WAFERS FOR CMOS LSI APPLICATIONS This specification technically approved by the Global Silicon Wafer Committee and is the dir…

SEMI M46-1101

Where

excess

is the capacitance of material in the

excess area,

is the wetted area,

is the illuminated area

13.2 Depletion Depth, W

, — calculated from the

parallel plate capacitor equation.

[µm]

13.3 Etched depth, W

— calculated from the charged

passed through the cell using Faraday’s law for

electrolysis.

FDA

Idte =

[µm]

Where

z is the effective dissolution valency,

F is the Faraday constant,

(= 9.65 × 10

Cmol

-1

)

D is the density of the semiconductor,

M is the molecular weight of the

semiconductor

I is the etch current

13.4 Total depth, W, — the sum of the depletion and

etch depths and is the depth at which the measurement

is made.

de=+ [µm]

14 Reporting Results

14.1 The following information shall be included in the

report:

14.1.1 Identification of Specimen — including details

of any pretreatment such as the use of a selective etch

to chemically etch the sample to the layer of interest.

14.1.2 Sealing Ring Area — both the wetted and

illuminated areas should be reported.

14.1.3 Electrolyte — the composition of the electrolyte

should specify the molecular concentration.

14.1.4 Material Constants — The relative permittivity

of the sample,

and the effective dissolution valency,

14.1.5 Primary Measurement Signal — the frequency

and amplitude of the signal used for the capacitance

measurement.

14.1.6 Secondary (bias) Signal — If the measurement

is made using a secondary modulation component its

frequency and amplitude should be reported. If the

measurement is made by changing the bias, its

minimum and maximum value should be specified.

14.1.7 Measurement Bias — The average value (DC

component) of the bias used during the capacitance

measurement.

14.1.8 Electrochemical Etching Bias — The bias used

to etch the sample including whether or not the sample

was illuminated. If etched at a constant current this

should be stated. Then it is not necessary to report the

bias.

14.1.9 Electrochemical Etching Current — If etched at

constant bias the average value of current measured

during electrochemical etching. If etched at a constant

current the value used.

NOTICE:. SEMI makes no warranties or

representations as to the suitability of the standards set

forth herein for any particular application. The

determination of the suitability of the standard is solely

the responsibility of the user. Users are cautioned to

refer to manufacturer’s instructions, product labels,

product data sheets, and other relevant literature

respecting any materials mentioned herein. These

standards are subject to change without notice.

The user’s attention is called to the possibility that

compliance with this standard may require use of

copyrighted material or of an invention covered by

patent rights. By publication of this standard, SEMI

takes no position respecting the validity of any patent

rights or copyrights asserted in connection with any

item mentioned in this standard. Users of this standard

are expressly advised that determination of any such

patent rights or copyrights, and the risk of infringement

of such rights, are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

the contents in whole or in part is forbidden without express writte

consent of SEMI.

SEMI M47-0704 © SEMI 2001, 2004 1

SEMI M47-0704

SPECIFICATION FOR SILICON-ON-INSULATOR (SOI) WAFERS FOR

CMOS LSI APPLICATIONS

This specification technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional

Standards Committee on April 30, 2004. Initially available at www.semi.org June 2004; to be published July

2004. Originally published November 2001; previously published March 2002.

1 Purpose

1.1 This specification defines thin-layer silicon-on-

insulator (SOI) wafer requirements for CMOS large

scale integrated circuit (LSI) devices. In another aspect,

this specification defines the generic characteristics of

SIMOX and bonded silicon-on-insulator wafers having

typically no more than 0.2 µm SOI layer thickness. By

defining parameters, inspection procedures and

acceptance criteria, both users and suppliers may

uniformly define product characteristics and quality

requirements.

2 Scope

2.1 This specification is specifically directed to

SIMOX and bonded silicon-on-insulator wafers, which

are exclusively used for LSI applications made up of

CMOS devices.

2.2 A complete purchase specification requires the

base silicon wafer, SOI surface and layer, and buried

oxide layer properties detailed in this standard, suitable

test methods for their characterization. SEMI M18 may

be for purchase specification purpose.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M1 — Specifications for Polished

Monocrystalline Silicon Wafers

SEMI M11 — Specifications for Silicon Epitaxial

Wafers for Integrated Circuit (IC) Applications

SEMI M18 — Format for Silicon Wafer Specification

From for Order Entry

SEMI M22 — Specifications for Dielectrically Isolated

(DI) Wafers

SEMI M34 — Guide for Specifying SIMOX Wafers

SEMI M35 — Guide for Developing Specifications for

Silicon Wafer Surface Features Detected by Automated

Inspection

SEMI M41 — Specification of Silicon-on Insulator

(SOI) for Power Device/ICs

SEMI MF26 — Standard Test Methods for

Determining the Orientation of a Semiconductive

Single Crystal

SEMI MF42 — Standard Test Methods for

Conductivity Type of Extrinsic Semiconductor

Materials

SEMI MF84 — Standard Test Method for Measuring

Resistivity of Silicon Wafers with an In-Line Four-

Point Probe

SEMI MF523 — Standard Practice for Unaided Visual

Inspection of Polished Silicon Wafer Surfaces

SEMI MF533 — Standard Test Method for Thickness

and Thickness Variation of Silicon Wafers

SEMI MF671 — Standard Test Method for Measuring

Flat Length on Wafers of Silicon and Other Electronic

Materials

SEMI MF928 — Standard Test Methods for Edge

Contour of Circular Semiconductor Wafers and Rigid

Disk Substrates

SEMI MF1152 — Standard Test Methods for

Dimensions of Notches on Silicon Wafers

SEMI MF1188 — Standard Test Method for Interstitial

Atomic Oxygen Content of Silicon by Infrared

Absorption

SEMI MF1241 — Standard Test Methods for

Terminology of Silicon Technology

SEMI MF1390 — Standard Test Method for Measuring

Warp on Silicon Wafers by Automated Noncontact

Scanning

SEMI MF1526 — Standard Test Method for Measuring

Surface Metal Contamination on Silicon Wafers by

Total Reflection X-Ray Fluorescence Spectroscopy

SEMI M47-0704 © SEMI 2001, 2004 2

SEMI MF1530 — Standard Test Method for Measuring

Flatness, Thickness, and Thickness Variation on Silicon

Wafers by Automated Noncontact Scanning

SEMI MF1619 — Standard Test Method for

Measurement of Interstitial Oxygen Content of Silicon

Wafers by Infrared Absorption Spectroscopy with p-

Polarized Radiation Incident at Brewster Angle

SEMI MF2074 — Standards Guide for Measuring

Diameter of Silicon and Other Semiconductor Wafers

3.2 ASTM Standards

E122 — Practice for Choice of Sample Size to Estimate

Average Quality of a Lot or Process

F1620 — Standard Practice for Calibrating a Scanning

Surface Inspection System Using Monodisperse

Polystyrene Latex Spheres Deposited on Polished or

Epitaxial Wafer Surfaces

3.3 JEITA Standards

JEITA EM-3602 — Standard Specification for

Dimensional Properties of Silicon Wafers with Specular

Surface

JEITA EM-3504

(JEIDA 61 in old version) —

Standard Test Method for Interstitial Atomic Oxygen of

Silicon by Infrared Absorption

JEITA EM-3505 — Height calibration in 1 nm order

for AFM

3.4 ANSI Standard

ANSI/ASQCZ1.4 — Sampling Procedure and Tables

for Inspection

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Terminology

4.1 Many terms relating to silicon technology are

defined in ASTM Terminology F 1241. Other terms

are defined as below.

4.2 Abbreviations and Acronyms

1 American Society for Testing and Materials, 100 Barr Harbor

Drive, West Conshohocken, Pennsylvania 19428-2959, USA.

Telephone: 610.832.9585, Fax: 610.832.9555 Website:

www.astm.org

2 Japanese Electronic and Information Technology Industries

Association, Tokyo Chamber of Commerce and Industry Bldg. 2-2,

Marunouchi 3-chome, Chiyoda-ku, Tokyo 100-0005, Japan. Website:

www.jeita.or.jp

3 Since a new number is assigned, it will be published soon. Until

then, an old version spec number is to be referred.

4 American National Standards Institute, New York Office: 11 West

42nd Street, New York, NY 10036, USA. Telephone: 212.642.4900;

Fax: 212.398.0023 Website: www.ansi.org

4.2.1 BOX — buried oxide layer

4.2.2 SIMOX — separation by implanted oxygen

4.3 Definitions

4.3.1 bonded interface — the plane where the bonding

between handle and device wafers takes place.

4.3.2 bonded wafer — an SOI wafer made by bonding

two silicon wafers with an insulating layer between

them. The insulating layer is typically thermally grown

oxide.

4.3.3 BOX pin-hole — electrically conductive path

through the BOX.

4.3.4 buried oxide layer — the silicon dioxide layer

between SOI layer and base silicon substrate.

4.3.5 handle wafer or base silicon wafer or base

silicon substrate — the substrate which structurally

supports the BOX and the SOI layer.

4.3.6 HF defect — defect in the SOI layer decorated by

immersing the wafer in HF for a certain time.

4.3.7 non-SOI edge area — an annulus between the

nominal radius of the surface silicon layer and the

nominal radius of the base silicon wafer (for bonded

SOI wafers). The annulus which implies an area is

determined by its width as one dimension. It is the

difference in the nominal radius of the surface silicon

layer and the base silicon wafer.

4.3.8 SIMOX wafer — SOI wafer made by oxygen

implantation technology

4.3.9 SOI etch pit — defect in an SOI layer decorated

by immersing the wafer in Secco etch solution.

4.3.10 SOI layer or surface silicon layer — the silicon

layer on the BOX of the SOI wafer.

4.3.11 void — local absence of SOI layer and/or BOX

in bonded wafer.

5 Ordering Information

5.1 Purchase orders for SIMOX or bonded silicon-on-

insulator wafers furnished to this specification shall

include the following items:

• Characteristics for the SOI layer (thickness, crystal

orientation, dopant, etc.)

• Characteristics for the base silicon substrate

(thickness, crystal orientation, dopant, etc.)

• Characteristics of the buried oxide (thickness,

dielectric breakdown voltage, etc.)

• Misalignment of wafer orientation between the SOI

layer and the handle wafer