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SEMI MF1725-1103 © SEMI 2003 3 NOTE 4: Staining may occur on heavily doped, p -type material with resistivit y of ≤ 0.1 Ω · cm, during dilution of th e polishing etch. Rapid transfer to fresh polish etch for less than 30…

SEMI MF1725-1103 © SEMI 2003 2

6 Apparatus

6.1 Slicing Equipment — Suitable for removing wafers

of varied thickness from ingots.

6.2 Lapping or Grinding Equipment (optional) —

Suitable for removing saw damage.

6.3 Laboratory Equipment — Suitable for use with

hydrofluoric acid (fluorocarbon, polyethylene, or

polypropylene beakers, graduates, pipettes, and

nonmetallic wafer pickup tools).

6.4 Acid Sink — In a fume hood and facilities for

disposing of acids and their vapors.

6.5 Personnel Safety Equipment — For handling acids,

such as gloves, safety glasses, face shield, and gown.

7 Reagents and Materials

7.1 Purity of Reagents — All chemicals for which such

specifications exist shall conform to the assay and

impurity levels of Grade 1 SEMI Specifications. Other

grades may be used provided it is first ascertained that

the reagent is of sufficiently high purity to permit its

use without lessening the accuracy of the determination.

7.2 Purity of Water — Reference to water shall be

understood to mean Type E-3 or better water as

described in ASTM Guide D 5127.

7.3 Chemical Polishing Solution — A variety of

chemical polishing solutions exist. Those listed in

Table 1 have been found to produce satisfactory results.

Table 1 Volume Proportions

Formulation Nitric Acid,

(Assay:

> 99.7%)

Hydrofluoric

Acid,

(Assay:

49 ± 0.25%)

Acetic Acid,

(Assay: 70

to 71%)

A 6 1 1

B 5 3 3

C 5 10 14

D 5 1 2

7.4 An aqueous, nonionic surfactant detergent solution.

8 Safety Precautions

8.1 The chemicals used in polishing etches are

potentially harmful and must be handled in a chemical

exhaust fume hood, with the utmost care.

8.2 Hydrofluoric acid solutions are particularly

hazardous and the specific preventive measures must be

strictly observed.

8.3 Safety or protective gear should be worn while

handling these acid solutions or their components.

Safety requirements vary, but the essentials are: plastic

gloves, safety glasses, face shield, acid gown, and shoe

covers.

9 Procedure

9.1 Sample Selection — Take the sample for evaluation

from the crystal close to the discarded crystal portion

found at the last of the solidified crystal. Other samples

may be specified in producer-consumer relationships.

NOTE 1: Determination of the most logical point of sample

selection may be established by inspection of the bottom taper

of the crystal. If the crystal has a complete bottom taper, then

the sample should be obtained from the last point of a full

crystal diameter. If the crystal has lost zero dislocation

growth before the formation of a tapered bottom, obtain the

sample 1–crystal diameter above the point of lost zero

dislocation structure.

9.2 Orient the ingot to be sliced with either the x-ray or

optical method of SEMI MF26 so that the surface to be

exposed is within 5° of the desired plane. Slice a wafer,

0.5- to 2-mm thick, from the crystal. Identify ingot

growth lines on the sample by a mark or a ground flat

for future reference in counting defects.

NOTE 2: Defects observed by preferential etching may be

increasingly distorted as misalignment from the major

crystallographic plane increases.

9.3 Remove the residual saw damage by mechanical

lapping and chemical polishing or by chemical

polishing alone.

9.3.1 Wash the as-cut or lapped wafer in a nonionic

surfactant detergent solution and rinse thoroughly in

water. Drying may be hastened by use of a lint-free

paper towel. The surface must be uniformly matte in

appearance with no scratches, wax, dirt or water stains.

9.3.2 Chemical Polish

9.3.2.1 Place the sample in the bottom of a

hydrofluoric acid resistant beaker with the side to be

inspected facing upward. The beaker diameter need

only be larger than the wafer diameter.

9.3.2.2 Pour the room temperature chemical polish etch

(from Section 7.3) until the surface of the sample is

covered with about 1 cm of solution.

9.3.2.3 Agitate during etching to reduce bubble

formation and surface artifacts.

NOTE 3: The polish etch procedure in Section 9.3 describes

a facility for evaluation of a small number of samples. More

sophisticated facilities are used in commercial environments.

9.3.2.4 Rapidly dilute the etching solution with water

and flush the solution from the beaker after the sample

wafer develops mirror-polished surfaces.

SEMI MF1725-1103 © SEMI 2003 3

NOTE 4: Staining may occur on heavily doped, p-type

material with resistivity of ≤ 0.1 Ω·cm, during dilution of the

polishing etch. Rapid transfer to fresh polish etch for less

than 30 s additional etching, followed by rapid flushing of the

polish etch can reduce silicon staining. If necessary, dilution

of the polishing etch with nitric acid flushing with water is

also effective in reducing stains.

9.3.2.5 Dry with filtered air or nitrogen after thorough

rinsing of the polish-etched sample.

9.4 Select an appropriate etching solution to decorate

the defects.

9.4.1 Refer to SEMI MF1809 to select an appropriate

etching solution.

9.4.2 Etch the samples to remove an amount of silicon

from the surface being evaluated, as agreed upon

between the parties to the test. If no removal amount is

defined, remove 5 to 15 µm of silicon from the surface

being evaluated.

9.5 Evaluate the preferentially etched sample in two

stages, macroscopic and microscopic.

9.5.1 Macroscopic Inspection — Use a high intensity

light, such as that specified in SEMI MF523, to inspect

the full sample surface. The characteristic patterns of

slip defects as shown in Figure 1 are easily identified in

macroscopic inspection. If evidence exists of

mechanically or handling induced damage or

contamination, repeat Sections 9.3 to 9.5 .

9.5.2 Microscopic Defect Counting — Count and

report the density of observed defects using

SEMI MF1810.

10 Keywords

10.1 dislocation; grain boundaries; ingot;

polycrystalline imperfections; preferential etch; silicon;

slip

NOTICE: SEMI makes no warranties or

representations as to the suitability of the standards set

forth herein for any particular application. The

determination of the suitability of the standard is solely

the responsibility of the user. Users are cautioned to

refer to manufacturer' s instructions, product labels,

product data sheets, and other relevant literature,

respecting any materials or equipment mentioned

herein. These standards are subject to change without

notice.

By publication of this standard, Semiconductor

Equipment and Materials International (SEMI) takes no

position respecting the validity of any patent rights or

copyrights asserted in connection with any items

mentioned in this standard. Users of this standard are

expressly advised that determination of any such patent

rights or copyrights, and the risk of infringement of

such rights are entirely their own responsibility.

{100} {111}

NOTE: The orientation of the wafer defines the location and

direction of the line defects.

Figure 1

Slip Defects as Seen with Macroscopic High-

Intensity Light Inspection

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

the contents in whole or in part is forbidden without express written

consent of SEMI.

SEMI MF1726-1103 © SEMI 2003 1

SEMI MF1726-1103

PRACTICE FOR ANALYSIS OF CRYSTALLOGRAPHIC PERFECTION

OF SILICON WAFERS

This standard was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the North American Silicon Wafer Committee. Current edition approved for publication by

the North American Regional Standards Committee on September 3, 2003. Initially available at

www.semi.org October 2003; to be published November 2003. Originally published by ASTM International

as ASTM F 1726-97. Last previous edition ASTM F 1726-02.

1 Purpose

1.1 The use of silicon crystals in many semiconductor

devices requires a consistent atomic lattice structure.

Crystal defects disturb local lattice energy conditions

that are the basis for semiconductor behavior. These

defects have distinct effects on essential semiconductor-

device manufacturing processes such as alloying and

diffusion.

1.2 Epitaxial growth processes are used extensively in

the manufacture of silicon electronic devices. Stacking

faults introduced during epitaxial growth can cause

“soft” electrical characteristics and preferential micro

plasma breakdowns in diodes.

1.3 Epitaxial defects are more clearly delineated with

the use of this destructive etching procedure. Epitaxial

wafers may however be classified nondestructively by

this method without the destructive preferential etching

and inspection steps.

1.4 This practice provides guidance regarding proce-

dures for analysis of crystal defects of silicon ingots

from which silicon wafers are cut.

1.5 This practice, together with the referenced

standards, may be used for process control, research

and development, and material acceptance purposes.

2 Scope

2.1 This practice covers the determination of the

density of crystallographic defects in unpatterned

polished and epitaxial silicon wafers. Epitaxial silicon

wafers may exhibit dislocations, hillocks, shallow pits

or epitaxial stacking faults, while polished wafers may

exhibit several forms of crystallographic defects or

surface damage. Use of this practice is based upon the

application of several referenced standards in a

prescribed sequence to reveal and count microscopic

defects or structures.

2.2 This practice is suitable for use with epitaxial or

polished wafers grown in either [111] or [100] direction

and doped either p or n-type with resistivity greater

than 0.005 Ω·cm.

2.3 This practice is suitable for use with epitaxial

wafers with layer thickness greater than 0.5 µm.

2.4 Additional requirements on the material to be

tested are listed in SEMI MF1810.

NOTICE: This standard does not purport to address the

safety issues, if any, associated with its use. It is the

responsibility of the user of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI MF95 — Test Method for Thickness of Lightly

Doped Silicon Epitaxial Layers on Heavily Doped

Silicon Substrates Using an Infrared Dispersive

Spectrophotometer

SEMI MF523 — Practice for Unaided Visual

Inspection of Polished Silicon Wafers Surfaces

SEMI MF1241 — Terminology of Silicon Technology

SEMI MF1809 — Guide for Selection and Use of

Etching Solutions to Delineate Structural Defects in

Silicon

SEMI MF1810 — Test Method for Counting

Preferentially Etched or Decorated Surface Defects in

Silicon Wafers

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Terminology

4.1 Defect-related terminology may be found in

SEMI MF1241.

5 Summary of Practice

5.1 Clean, unprocessed polished or epitaxial wafers are

selected. The wafers are examined under bright light

illumination to ensure that they are free from

contamination and obvious surface damage. Epitaxial

1 Currently available in Annual Book of ASTM Standards, Vol 10.05.

These documents have been transferred to SEMI, and will appear in

SEMI Standards Publications beginning with the November 2003

edition.