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SEMI G80-0200 © SE MI 2000 1 SEMI G80-0200 TEST METHOD FOR THE ANALYSIS OF OVERA LL DI GITAL TIMING ACCURACY FOR AUTOMATED TEST EQUIPMENT This test method was te chnically approved by the G lobal A u tom ated Te st Equip…

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SEMI G79-0200 © SEMI 20005
control timing edge, any Z transition format, and any
test cycle length.
NOTE 3: This definition does not include I/O timing
restrictions imposed by the round trip delay between the tester
electronics and the DUT.
Conditions:
• delays are normalized to pin1 (first tester pin),
rising edge, NR format, 5V, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load C; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
7.1.6 Input Timing Delay Error for Drive High/Low to
Z — Time delay error at the midpoint of a driver
transition from high/low to Z, with respect to an ideal
delay, using any pin, any delay value, any Z control
timing edge, any Z transition format, and any test cycle
length.
NOTE 4: This definition does not include I/O timing
restrictions imposed by the round trip delay between the tester
electronics and the DUT.
Conditions:
• delays are normalized to pin1 (first tester pin),
rising edge, NR format, 5V, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load C; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
NOTICE: SEMI makes no warranties or represent-
ations as to the suitability of the standard set forth
herein for any particular application. The determination
of the suitability of the standard is solely the
responsibility of the user. Users are cautioned to refer
to manufacturer’s instructions, product labels, product
data sheets, and other relevant literature respecting any
materials mentioned herein. These standards are
subject to change without notice.
The user’s attention is called to the possibility that
compliance with this standard may require use of copy-
righted material or of an invention covered by patent
rights. By publication of this standard, SEMI takes no
position respecting the validity of any patent rights or
copyrights asserted in connection with any item
mentioned in this standard. Users of this standard are
expressly advised that determination of any such patent
rights or copyrights, and the risk of infringement of
such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI G80-0200 © SEMI 20001
SEMI G80-0200
TEST METHOD FOR THE ANALYSIS OF OVERALL DIGITAL TIMING
ACCURACY FOR AUTOMATED TEST EQUIPMENT
This test method was technically approved by the Global Automated Test Equipment Committee and is the
direct responsibility of the North American Automated Test Equipment Committee. Current edition approved
by the North American Regional Standards Committee on September 3, 1999. Initially available at
www.semi.org December 1999; to be published February 2000.
1 Purpose
1.1 This procedure will define a standard process
whereby any logic integrated circuit (IC) ATE system
can be evaluated for parameters that makeup an AC
timing accuracy specification.
1.2 Application of this procedure will simplify ATE
comparisons, reduce specification ambiguity, simplify
user acceptance procedures, simplify ATE performance
monitoring, and provide a common validation criteria
for ATE suppliers.
2 Scope
2.1 This procedure is intended for analysis of timing
accuracy specifications for all semiconductor automatic
test equipment (ATE) capable of digital functional
testing. The extent of the analysis includes overall
timing accuracy and the primary components of overall
timing accuracy as defined in the definition section of
this document.
2.2 This procedure does not include analysis of the
following parameters associated with ATE timing
accuracy:
• minimum driver pulse width,
• comparator bandwidth,
• I/O round trip delay,
• test fixturing errors,
• device insertion errors,
• time measurement unit (TMU) accuracy, and
• ATE capability or performance beyond AC timing
accuracy.
2.3 Application of this procedure can reduce
equipment acceptance time resulting in savings for both
the end-users and ATE suppliers.
2.4 This standard does not purport to address safety
issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory limitations prior to use.
3 Limitations
3.1 The following limitations are inherent to this
procedure:
3.1.1 The tolerances of each measurement used in the
procedure are listed in each test, where appropriate.
3.1.2 The verification methods do not include varying
environmental conditions, so results may not reflect
performance at environmental limits.
3.1.2.1 Due to execution time limits, the verification
procedure does not represent an exhaustive analysis.
The number of data points analyzed is intended to pro-
vide a minimum representative assessment of AC tim-
ing accuracy parameters in a practical amount of time.
3.1.3 This method uses only edge compare mode and
non-multiplexed operation in providing a minimum
representative assessment of AC timing accuracy.
3.1.4 This method does not determine the effects that
duty cycle variations have on AC timing accuracy.
3.1.5 Not being an exhaustive analysis this method
avoids comprehensive testing as might be expected for
complex AC timing functions such as on-the-fly (OTF)
timing. This method was defined with the intention of
keeping the data gathering practical such that
meaningful results are obtained in a reasonable amount
of time. In the case of timing-on-the fly a routine is
contained in this method and can be used as a reference
parameter for comparative purposes when systems with
on-the-fly timing are analyzed. Thus only the most
fundamental AC timing results are produced and OTF
timing is not included as part of the overall timing
accuracy (OTA) results.
3.1.6 Discretion is advised when interpreting OTA
results obtained from this method. Self-analysis cannot
allow for all error components to be isolated. Thus good
(compliant) method results should be viewed with cau-
tion as potentially compliant. On the other hand, poor
(non-compliant) method results are a strong indication
that the system under evaluation is questionable
regarding its accuracy and most likely non-compliant.
SEMI G80-0200 © SEMI 2000 2
4 Referenced Standards
4.1 SEMI Standard
SEMI G79 –– Specification for Overall Digital Timing
Accuracy
5 Terminology
5.1 Abbreviations and Acronyms
5.1.1 1
1
— tester output driver high level
5.1.2 0
2
— tester output driver low level
5.1.3 ATE — automated test equipment
5.1.4 DUT — device under test
5.1.5 H
3
— tester input comparator expect high level.
5.1.6 L
4
— tester input comparator expect low level.
5.1.7 n — highest pin/channel number, and Pin 1 ––
refers to the lowest pin/channel number.
5.1.8 NR — non-return signal format
5.1.9 RTO — return to one signal format.
5.1.10 RTZ — return to zero signal format.
5.1.11 SBC — surround by complement signal format.
5.1.12 Z — tester output driver high i mpedance (“off”)
state.
5.2 Definitions
5.2.1 device insertion errors — error influenced by
device-input capacitance and/or terminations.
5.2.2 edge — time delay created by an ATE delay
generation resource.
5.2.3 high bandwidth oscilloscope — digital sampling
oscilloscope with > 10 GHz bandwidth, using probes
with > 1 GHz bandwidth, 500 ohm input impedance,
2.5pF ± 0.5pF input capacitance and < 0.125" ground
lead.
5.2.4 pin — tester channel
5.2.5 performance board — printed circuit board used
to interface the tester channels to the device under test.
5.2.6 test fixturing errors — error influenced by mis-
matched signal path lengths, impedance discontinuities,
lumped capacitance/inductance elements, and high
frequency loss due to skin effect or interconnects.
1 This convention is not universal. Sometimes a “H” is used.
2 This convention is not universal. Sometimes a “L” is used
3 This convention is not universal. Sometimes a “1” is used.
4 This convention is not universal. Sometimes a “0” is used.
5.2.7 window compare — monitor device contin-
uously during a time interval.
5.2.8 zero_reference_measurement — oscilloscope
measurement of the midpoint of a 0–3v NR signal
rising edge with delay = 0s. This is an arbitrary
reference signal selected by the user of this method.
The method user is free to choose a convenient
reference signal that will allow consistent use of that
signal for making edge placement timing measurements
during tests described in level 2 of this procedure.
6 Summary of Method
6.1 This procedure provides a hierarchical, generic
method of analyzing ATE timing accuracy. The
hierarchy supports two levels of specification analysis.
Broad, composite net results are available by using the
ATE for self-analysis in Level 1.
6.2 At this level, a large amount of data can be effi-
ciently collected, representing the net conformance to
overall timing accuracy specifications. This technique,
however, precludes isolation and detailed analysis of
specific accuracy components. Therefore, a second
level of analysis, incorporating external instruments is
included. While the first level provides efficient, broad
analysis, the second level provides less efficient,
detailed analysis.
6.3 Results from the analyses are saved in a standard
format to facilitate further use for application specific
data reduction. The minimum format is:
test #, channel #, min value, max value
6.3.1 Verification Procedure Summary
6.3.1.1 Level 1 ATE Self-Analysis
• Highly Efficient
• Broad Scope
• Moderate Error Observability
• Drive Input to Compare Output Tests
• 3 Voltages
• 2 Pin Directions
• 503 Test Cycles
5
• 503 Pulse Widths
• 12 Transitions
6
•
4 Formats
• Extended Delay Tests
5 Reference Figure 3.
6 Reference Figure 2.