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SEMI G61-94 © SEMI 1994 1 SEMI G61-94 SPECIFICA TION FOR COFIRED CERA M IC PACKAGES 1 Preface 1.1 Pur pose — This specification d e fi nes the materials and acceptance criteria f or high-temperature, cofired ceramic pack…
SEMI G60-94 © SEMI 1994, 2002 3
13.2 Vendor’s lot number for the interleaf material,
and date of shipment.
13.3 Sample conditioning conditions.
13.4 Test conditions if different from this test method.
13.5 The surface charged.
13.6 Results from Section 11 indicating the calculated
decay time for each specimen in the sample for both the
positive and negative charges and the acceptance (or
rejection) at incoming inspection. SPC charting
techniques may be used to monitor results.
NOTE 5: Acceptance/rejection limits shall be agreed between
user and supplier.
Figure 1
Electrostatic Test Chamber
High Voltage Source
Electrometer
Recorder
Three (3) Positional
Control Switch
Electrostatic Test
Chamber See Figure 1
Electrostatic Test Unit
Figure 2
Electrostatic Test Arrangement
14 Related Documents
14.1 The following documents provide additional
information for testing electrostatic properties. The test
method described in this document is based on FED-
STD-101C.
14.2 Electronic Industries Association
1
EIA-541 — Packaging Materials Standards for ESD
Sensitive Items
14.3 Federal Specifications
2
FED-STD-101C — Test Procedures for Packaging
Items
14.4 JIS Specifications
3
JIS K6911 — Testing Methods for Thermosetting
Plastics
JIS L 1094 — Testing Methods for Electrostatic
Propensity of Woven and Knitted Fabrics
NOTICE: These standards do not purport to address
safety issues, if any, associated with their use. It is the
responsibility of the user of these standards to establish
appropriate safety and health practices and determine
the applicability of regulatory limitations prior to use.
SEMI makes no warranties or representations as to the
suitability of the standards set forth herein for any
particular application. The determination of the
suitability of the standard is solely the responsibility of
the user. Users are cautioned to refer to manufacturer’s
instructions, product labels, product data sheets, and
other relevant literature respecting any materials
mentioned herein. These standards are subject to
change without notice.
The user’s attention is called to the possibility that
compliance with this standard may require use of
copyrighted material or of an invention covered by
patent rights. By publication of this standard, SEMI
takes no position respecting the validity of any patent
rights or copyrights asserted in connection with any
item mentioned in this standard. Users of this standard
are expressly advised that determination of any such
patent rights or copyrights, and the risk of infringement
of such rights, are entirely their responsibility.
1 Electronic Industries Alliance, EIA Engineering Department,
Standards Sales Office, 2001 Eye Street, NW, Washington, D.C.
20006, USA. Website: www.eia.org
2 Federal Specifications, GSA Specifications and Consumer
Information Branch, Bldg. 197, Washington Navy Yard, Washington,
DC 20407
3 Japanese Industrial Standards, Available through the Japanese
Standards Association, 1-24, Akasaka 4-Chome, Minato-ku, Tokyo
107-8440, Japan. Telephone: 81.3.3583.8005; Fax: 81.3.3586.2014
Website: www.jsa.or.jp
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express writte
n
consent of SEMI.
SEMI G61-94 © SEMI 19941
SEMI G61-94
SPECIFICATION FOR COFIRED CERAMIC PACKAGES
1 Preface
1.1 Purpose — This specification defines the materials
and acceptance criteria for high-temperature, cofired
ceramic packages.
1.2 Scope — The criteria detailed in this specifiication
apply to the following package outlines registered with,
or specified by JEDEC (see Publication 95), EIAJ, or
MIL-STD-1835 specifications:
Chip Carriers (Leadless or Leaded)
Dual-in-Line Packages (Sidebrazed)
Flat Packs (Top or Bottom Brazed)
Grid Arrays (Land/Ball or Pin)
NOTE 1: Packages not meeting these specifications may also
use the criteria as appropriate.
This document consolidates the criteria for all cofired
packages so that package amnufacturing and inspection
may be simplified and costs reduced.
1.3 Units — U.S. Customary (inch -pound) or metric
(SI) units may be used at the customer’s discretion.
This specification uses U.S. Customary units as the
prime unit. In the drawings, only U.S. Customary units
are detailed.
2 Applicable Documents
2.1 Order of Precedence — To avoid conflicts, the
order of precedence when ordering packages shall be as
follows:
Purchase Order
Customer’s Package Drawings
This Specification
Reference Documents
Related Documents
2.2 Referenced Documents
2.2.1 SEMI Specifications
SEMI G6 — Seal Ring Flatness
SEMI G8 — Gold Plating — Temperature Resistance
SEMI G23 — Measuring the Inductance of Package
Leads
SEMI G24 — Measuring the Lead-to-Lead and Loading
Capacitance of Package Leads
SEMI G25 — Measuring the Resistance of Package
Leads
SEMI G30 — Test Method, Junction-to-Case Thermal
Resistance Measurements on Ceramic Packages
SEMI G35 — Test Methods for Lead Finishes on
Semiconductor (Acitve) Devices
2.2.2 ANSI Specifications
1
ANSI Y14.5M — Dimensioning and Tolerancing
2.2.3 ASTM Specifications
2
ASTM B 568 — Measurement of Coating Thickness by
X-Ray Spectrometry
ASTM E 18 — Test Methods for Rockwell Hardness
and Rockwell Superficial Hardness of Metallic
Materials
ASTM E 165 — Liquid Penetrant Inspection Method
ASTM E 384 — Test Method for Microhardness of
Materials
ASTM F 109 — Surface Imperfections on Ceramics
2.2.4 JEDEC Specifications
3
Pub. No. 95 — Registered and Standard Outlines for
Semiconductor Devices
2.2.5 Military and Federal Specifications
4
MIL-STD-7883 — Brazing
MIL-STD-38510 — General Spec. for Microcircuits
MIL-G-45204 — Gold Plating — Electrodeposited
QQ-N-290A — Nickel Plating (Electrodeposited)
2.2.6 EIAJ Specifications
2.3 Related Documents
2.3.1 Military and Federal Specifications
MIL-STD-105 — Sampling Procedures and Tables for
Inspection by Attributes
1 ANSI, 1430 Broadway, New York, NY 10018
2 American Society of Testing Materials, 100 Barr Harbor Drive,
West Conshohoken, PA 19428-2959
3 JEDEC, 2001 Eye Street N.W., Washington D.C. 20006
4 Military Standards, Naval Publications and Form Center, 5801
Tabor Avenue, Philadelphia, PA 19120
SEMI G61-94 © SEMI 1994 2
3 Definition of Terms
3.1 blister (bubble) ceramic — an enclosed, localized
separation within or between the layers of a ceramic
package that does not expose an underlying layer of
ceramic or metallization.
3.2 blister (bubble) metallization — an enclosed,
localized separation of a metallization layer from its
base material (such as ceramic or another metal layer)
that does not expose the underlying layer.
3.3 braze — in semiconductor pac kages, an alloy used
to attach pins, leads, seal rings and heat sinks/studs to
the package.
3.4 burr — an adherent fragment of parent material at
a component edge. In leadframes, the metal burr, due to
the stamping operation, may be in the horizontal or
vertical direction to the surface. In ceramic packages,
this type of characteristic is called a fin.
3.5 castellations — metallized sem i-circular channels
on chip carrier edges which provide contact between
internal package metallization traces and the external
test pads. These castellations provide for improved
solder fillets during attachment to a circuit board (see
Figure 1).
3.6 cavity-down packages — packages where the die
surface faces the mounting board. (See Figure 2 for the
pin grid array packages in the cavity-down
configuration. It is more usual to refer to the chip
carrier mounting surfaces as the seating planes. In this
cavity orientation, the seating plane is Seating Plane 2
per JEDEC JC-11.)
3.7 cavity-up packages — package s where the die
surface faces away from the mounting board (see
Figure 2 or Seating Plane 1 for chip carriers).
3.8 chip — region of material mis sing from a
component (e.g., ceramic from a package, or solder
from a preform). The region does not progress
completely through the component and is formed after
the component is manufactured. Chip size is defined by
its length, width and depth from a projection of the
design platform. Also called chipout (see Figure 1).
3.9 co-fired — in the manufacturing of some types of
ceramic packages, the technology used to join together
various ceramic layers and metallization patterns
screened onto those layers by simultaneous firing at
high temperature.
3.10 contact pad — in a leadless ch ip carrier or land
grid array, the metallized areas on the bottom of the
package that provide contact point between the internal
leads and connecting external circuitry. They are also
used for electrical test pads.
3.11 crack — a cleavage or fracture that extends to the
surface of a semiconductor package or solder preform.
The crack may or may not pass through the entire
thickness of the package or preform.
3.12 critical seal area (ceramic) — on a
semiconductor package, the area bounded by the
shortest nominal design distance from the largest
cavity, usually the wire bond cavity, to the edge of the
package or ceramic layer forming the seal area.
3.13 critical seal area — metallizat ion or metal ring
— The entire area of the seal ring; it applies to plated
refractory metal or a metal ring.
3.14 critical seal path (ceramic) — on a
semiconductor package, the shortest nominal design
distance from the largest cavity, usually the wire bond
cavity, to the edge of the package or ceramic layer
forming the seal area.
3.15 delamination — in a co-fired ceramic package,
chip carrier, pin grid array, etc., the separation of one
ceramic layer from another.
3.16 element (packaging) — part of a semiconductor
package feature (e.g., package leads have braze
paddle/stand-off and contact elements, pins have the
nail head/braze area and contact elements).
3.17 fin — on a ceramic package or cap, a fine
feathery-edged projection of parent ceramic material on
the corner of the ceramic body.
3.18 flatness — in a ceramic package or leadframe,
the allowable deviation of a surface from a defined
reference plane. The tolerance zone is defined by two
parallel planes within which the surface must lie.
3.19 foreign material — an adheren t particle that is
not parent material of the component. Adherence means
that the particle cannot be removed by an air or nitrogen
blast at 20 psi.
3.20 heat exchange area — a metal lized region on one
major surface of the package to which heat sinks may
be attached by brazing, soldering, or adhesive resin.
3.21 layer — on a cofired ceramic package, the body
is made from layers of ceramic or metallized ceramic.
The layers are defined by their functionality, and
several ceramic layers may be described as comprising
one functional layer if all are common in plan-form and
function (e.g., die attach cavity) (see Figure 4).
3.22 lead offset — in brazed lead ceramic packages,
the variation in position of the centerline of the lead
with reference to the centerline of the braze pad to
which it is mounted.
3.23 lead sweep — lead movement, measured with
respect to a datum, perpendicular to the top or bottom