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SEMI E129-1103 © SEMI 2003 14 RELATED INFORMATION 1 DEVICE SENSITIVIT Y MEASUREMENTS NOTICE: The m aterial contained i n this rela ted inform ation is not a n official part of SEMI E129 and is not intended to m odify or …

SEMI E129-1103 © SEMI 2003 13

A1-2.7 Guide Recommendations

A1-2.7.1 This document recommends the values

shown in parentheses in the second column of Table

A1-8 of this Appendix and includes them in Section

12.5 Table 1.

A1-2.8 Guide Recommendations for Equipment

Malfunctions

A1-2.8.1 Most semiconductor manufacturing

equipment should comply with the ESD immunity

requirements of the European Economic Community

(EEC). The testing mandated by the EEC uses the test

methods and ESD immunity levels specified in IEC/TS

61000-4-2. To test for compliance, measurements are

made with an ESD simulator described by IEC/TS

61000-4-2. Equipment is required to pass a test

involving the discharge produced by a 150-pF capacitor

charged to 4000 V, or 600 nC.

A1-2.8.2 Users should note that the above test

discharge level and properties (i.e. discharge voltage,

discharge model and pulse rise time) may not be

sufficient to predict actual discharges that occur in

semiconductor production environments. In addition,

the ESD immunity of equipment in an isolated test

environment may change when it is installed in a

production environment.

A1-2.8.3 The discharge test specified in IEC/TS

61000-4-2 is done at significantly higher charge levels

than are recommended for objects in the facility in

Table A1-2 of this Appendix. If the recommendations

of Table A1-2 are followed, static charge levels should

be low enough to prevent ESD-induced equipment

malfunctions.

A1-2.8.4 If the recommended electrostatic levels

regarding ESD contained in Section 12.5 Table 1 are

not used, those contained in SEMI E78 should be used

for equipment.

A1-3 References

SEMI E78 — Electrostatic Compatibility

– Guide to

Assess and Control Electrostatic Discharge (ESD) and

Electrostatic Attraction (ESA) for Equipment

Montoya, J. A., Levit, L., and Englisch, A., “A Study of

the Mechanisms of ESD Damage for Reticles”,

Electrical Overstress/Electrostatic Discharge

Symposium Proceedings, 394-405 (2000)

Cooper, D. W., Miller, R. J., Wu, J. J., and Peters, M.

H., "Deposition of Submicron Aerosol Particles During

Integrated Circuit Manufacturing: Theory", Particulate

Sci. Technol. 8 (3 and 4): 209-224 (1990)

Liu, B. Y. H., and Ahn, K. H., "Particle Deposition on

Semiconductor Wafers", Aerosol Sci. Technol. 6: 215 -

224 (1987)

International Technology Roadmap for Semiconductors

(1999, 2002, 2003)

ISO 14644 – Cleanrooms and Associated Controlled

Environments – Part 1 – Classification of Air

Cleanliness

NOTICE: SEMI makes no warranties or

representations as to the suitability of the standards set

forth herein for any particular application. The

determination of the suitability of the standard is solely

the responsibility of the user. Users are cautioned to

refer to manufacturer’s instructions, product labels,

product data sheets, and other relevant literature

respecting any materials mentioned herein. These

standards are subject to change without notice.

The user’s attention is called to the possibility that

compliance with this standard may require use of

copyrighted material or of an invention covered by

patent rights. By publication of this standard, SEMI

takes no position respecting the validity of any patent

rights or copyrights asserted in connection with any

item mentioned in this standard. Users of this standard

are expressly advised that determination of any such

patent rights or copyrights, and the risk of infringement

of such rights, are entirely their own responsibility.

8 International SEMATECH, 2706 Montopolis Drive, Austin, TX

78741, USA (www.sematech.org)

9 Institute of Environmental Sciences and Technology (IEST), 5005

Newport Drive, Rolling Meadows, IL, 60008-38411, USA

(www.iest.org)

SEMI E129-1103 © SEMI 2003 14

RELATED INFORMATION 1

DEVICE SENSITIVITY MEASUREMENTS

NOTICE: The material contained in this related information is not an official part of SEMI E129 and is not

intended to modify or supersede the guide in any way. These notes are provided as a source of information to aid in

the application of the guide, and are to be considered reference material. Determination of the suitability of the

material is solely the responsibility of the user. This related information was approved by full letter ballot

procedures on September 3, 2003.

R1-1 ESD Damage

R1-1.1 Introduction

R1-1.1.1 ESD damage to devices occurs when they

come into contact with personnel and facility or

equipment surfaces. Either may store a residual charge

large enough to destroy the device if a discharge occurs.

It is also possible that charge stored on insulating parts

of products or reticles will induce charges on their

conductive parts. Discharges may occur between

conductive parts at different potentials or when the

conductive parts touch ground. The same types of

induced charge can be produced when products or

reticles are placed in the electrostatic field produced by

static charge on facility or equipment surfaces that are

insulative or isolated from ground. In the

semiconductor industry, it has been established that

significant proportions of customer field returns are

attributed to damage resulting from ESD.

R1-1.2 Description of ESD Damage Mechanisms

R1-1.2.1 ESD failures are the result of either a current-

induced phenomenon or a charge-induced phenomenon,

and the damage can either be junction, contact,

dielectric or oxide related. The apparent similarity in

current-induced damage resulting from ESD due to

human body model (HBM) discharges or machine

model (MM) discharges results from the thermal nature

of both of these processes. The HBM and MM

damages result when the temperature (joule heating) of

the region dissipating the ESD pulse energy reaches a

critical value and melting occurs.

R1-1.2.2 The charged device model (CDM) predicts

charge-induced phenomena. For CDM-type discharges,

oxide punch through occurs when the ESD voltage

applied across the oxide creates a high enough field to

break down the oxide. Excessive current flow results,

causing an oxide short, but there is no heat transfer

(adiabatic process). It should be noted here that the

time duration for typical ESD events from charged

objects and personnel ranges from 10 to 100 ns, while

CDM-type events occur in less than 1 ns.

R1-1.3 Device Testing Models

R1-1.3.1 Human Body Model (HBM) — The HBM is

the oldest and the most widely used of the three ESD

models. The model attempts to replicate the discharge

when a charged human touches a device that is at a

lower potential. Human capacitance and resistance

have been chosen to be 100 pF and 1500 Ω

respectively. The values were chosen after

measurements were made on humans in varying

positions with respect to their surroundings. The

resulting discharge waveform has a double exponential

shape with rise time range of 2–10 ns and a decay

constant (1/e position) of 150 ± 20 ns. The typical peak

currents range from 0.67 A at 1000 V to 2.67 A at 4000

R1-1.3.2 Machine Model (MM) — The MM is

described by the Electronic Industries Association of

Japan (EIAJ) as a worst-case HBM. The model

attempts to replicate the discharge from a metallic arm

of an automatic handler coming into contact with the

metallic leads of a semiconductor device. A

capacitance of 200 pF and ideally zero resistance

produces a sinusoidal decaying waveform with an

effective pulse duration of 200 ns. The typical peak

currents range from 1.75 A at 100 V to 14.0 A at 800 V.

Note that MM failures occur at 5–10 times lower

voltage than HBM.

R1-1.3.3 Charged Device Model (CDM) — The CDM

in its purest form is actually a field-induced model

because the device is actually part of model. This

model attempts to describe a device which itself

becomes charged due to an external field, or due to

triboelectric charging of the device surfaces. During

discharge the parasitics (i.e., capacitance, inductance

and impedance) in the device play a significant role in

the resulting failure. The discharge pulse is a sinusoidal

waveform with an extremely fast rise time of less than

500 ps. The waveform decays rapidly with a total pulse

duration of less than 5 ns. The peak currents range

from 2.0 A at 250 V charging voltage to 18.0 A at 2000

V charging voltage.

R1-1.3.4 Correlation Between Models — Whether or

not a correlation exists between HBM and MM is

debatable. While some companies report a correlation

SEMI E129-1103 © SEMI 2003 15

of roughly 10:1 between the two models, other

companies have seen anywhere from 5–20:1 differences

in passing voltages between the two models. There is

also no established voltage correlation between CDM

damage and HBM or MM ESD events. In equipment,

ESD damage events will be related to the MM or CDM

types of ESD. Users will need to determine the type of

ESD hazard to their devices and choose the test method

accordingly.

R1-2 ESD Laboratory Simulation Testing

R1-2.1 Description of Test Methods — Test procedures

discussed here for ESD simulation conform to those

established by the ESD STM5.1, ANSI ESD STM5.2,

ANSI ESD STM5.3.1 and MIL-STD 883 Method

3015.7. Details are to be found in these standards.

Devices are qualified at a level corresponding to the

highest ESD stress they are able to withstand.

R1-2.2 Simulation Test Results — In general all units

must be data-logged both pre- and post-stress test. Any

leakage current equal to or greater than a specific

amount (company dependent—typically 10 µA or less)

is “flagged” as a failure, and any current shift greater

than about 200 nA is marked on the record.

R1-2.3 HBM Stress Testing — A resistance-

capacitance (R-C) network is used to simulate the ESD

event. In an HBM ESD Simulator, a high voltage is

used to charge the capacitor (100 pF) which discharges

through the resistor (1500 Ω) into the device under test.

The present standard test method requires a minimum

of 2 discharges (i.e., 1 positive and 1 negative) per

voltage level.

R1-2.4 MM Stress Testing — An R-C network is also

used in the MM ESD Simulator for ESD testing. High

voltage charges the capacitor (200 pF) which

discharges through the short wire (~0 Ω) into the device

under test. The present standard requires a minimum of

6 discharges (i.e., 3 positive and 3 negative).

R1-2.5 CDM Stress Testing — The package and lead

frame of the device are charged by direct charging or

field induction.

R1-2.5.1 For the Direct Charging Method, direct

contact is made to one of the device leads connected to

the substrate or bulk material of the device. The device

is then discharged via a 1-ohm resistor to ground.

R1-2.5.2 For the Field Induced Method, the device is

placed on a metallic charging plate with the device

packaging material touching the plate. Applying a

voltage to the charging plate raises the potential of the

device. The induced voltage on the device is

discharged to ground through a 1-ohm resistor that

contacts each device lead. The present standard

requires a minimum of 6 discharges (i.e., 3 positive and

3 negative) from each device lead.

R1-3 References

R1-3.1 ESD Association Standards and Advisories

ANSI ESD STM5.2 — Electrostatic Discharge

Sensitivity Testing

– Machine Model

ANSI ESD STM5.3.1 — Charged Device Model

(CDM) – Component Level

ESD ADV11.2 — Triboelectric Charge Accumulation

Testing

ESD S6.1 — Grounding - Recommended Practices

ESD STM5.1 — Electrostatic Discharge Sensitivity

Testing – Human Body Model

ESD TR11-01 — Electrostatic Guidelines and

Considerations for Cleanrooms and Clean

Manufacturing

R1-3.2 JEDEC Documents

JESD22-A114 — Electrostatic Discharge (ESD)

Sensitivity Testing Human Body Model (HBM)

JESD22-C101 — Field-Induced Charged-Device

Model Test Methods for Electrostatic Discharge

Withstand Thresholds of Microelectronic Components

JESD625 — Requirements for Handling Electrostatic-

Discharge-Sensitive (ESDS) Devices

R1-3.3 Other Documents

ANSI IEEE STD 142 — IEEE Recommended Practice

for Grounding of Industrial and Commercial Power

Systems

ANSI/NFPA 70 — National Electrical Code

MIL-STD 883 — Test Method Standard Microcircuits

(Method 3015.7

– Electrostatic Discharge Sensitivity

Classification), Defense Supply Center Columbus, P.O.

Box 3990, Columbus, OH 43216-5000, USA

(

www.dscc.dla.mil)

Avery, L.R., “ESD Protection Structures to Survive the

Charged Device Model (CDM)”, Proceedings of the

EOS/ESD Symposium, Orlando, FL (1987), pp. 186-

191.

Avery, L.R., “Charged Device Model Testing: Trying

to Duplicate Reality”, Proceedings of the EOS/ESD

Symposium, Orlando, FL (1987), pp. 88-92.

Cook, C., Daniel, S., “Characterization and Failure

Analysis of Advanced CMOS Sub-Micron ESD

Protection Structures”, Proceedings of the EOS/ESD

Symposium, Dallas, TX (1992), pp. 149-157.