semi合集-English.pdf - 第5018页

SEMI M18-0704 © SEMI 1990, 2004 4 50433/1 — D eterminat ion of the Ori entation of Si ngle Crystals by Means of X-Ray Diffraction 50433/2 — D eterminat ion of the Ori entation of Si ngle Crystals by Means of Optical Refl…

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SEMI M18-0704 © SEMI 1990, 2004 3
SEMI MF1393 — Test Metod for Determining Net
Carrier Density Profile in Silicon Wafers by
Capacitance-Voltage Measurements with a Mercury
Probe
SEMI MF1451 — Standard Test Method for Measuring
Sori on Silicon Wafers by Automated Noncontact
Scanning
SEMI MF1526 — Standard Test Method for Measuring
Surface Metal Contamination on Silicon Wafers by
Total Reflection X-ray Fluorescence Spectroscopy
SEMI MF1530 — Standard Test Method for Measuring
Flatness, Thickness, and Thickness Variation on Silicon
Wafers by Automated Noncontact Scanning
SEMI MF1528 — Test Method for Measuring Boron
Contamination in Heavily Doped N-Type Silicon
Substrates by Secondary Ion Mass Spectrometry
SEMI MF1535 — Standard Test Method for Carrier
Recombination Lifetime in Silicon Wafers by
Noncontact Measurement of Photoconductivity Decay
by Microwave Reflectance
SEMI MF1617 — Standard Test Method for Measuring
Surface Sodium, Aluminum, and Potassium on Silicon
and EPI Substrates by Secondary Ion Mass
Spectroscopy
SEMI MF1619 — Standard Test Method for
Measurement of Interstitial Oxygen Content of Silicon
Wafers by Infrared Absorption Spectroscopy with p-
Polarized Radiation Incident at the Brewster Angle
SEMI MF1620 — Standard Practice for Calibrating a
Scanning Surface Inspection System Using
Monodisperse Polystyrene Latex Spheres Deposited on
Polished or Epitaxial Surfaces
SEMI MF1621 — Standard Practice for Determining
Positional Accuracy Capabilities of a Scanning Surface
Inspection System
SEMI MF1725 — Standard Guide for Analysis of
Crystallographic Perfection of Silicon Ingots
SEMI MF1726 — Standard Guide for Analysis of
Crystallographic Perfection of Silicon Wafers
SEMI MF1727 — Practice for Detection of Oxidation
Induced Defects in Polished Silicon Wafers
SEMI MF1809 — Guide for Selection and Use for
Etching Solutions to Delineate Structural Defects in
Silicon
SEMI MF1810 — Test Method for Counting
Preferentailly Etched or Decorated Structural Defects
on Silicon Wafers
SEMI MF1982 — Test Method for Analyzing Organic
Contamination on Silicon Wafers Surfaces by Thermal
Desporption Gas Chromatography
SEMI T1 — Specification for Back Surface Bar Code
Marking of Silicon Wafers
SEMI T2 — Specification for Marking of Wafers with
a Two-Dimensional Matrix Code Symbol
SEMI T6 — Procedure and Format for Reporting of
Test Results by Electronic Data Interchange (EDI)
SEMI T7 — Specification for Back Surface Marking of
Double-Side Polished Wafers with a Two-Dimensional
Matrix Code Symbol
3.2 ANSI Standard
1
ANSI/ASQC Z1.4 — Sampling Procedures and Tables
for Inspection by Attributes
3.3 ASTM Standards
2
D 523 — Standard Test Method for Specular Gloss
E 122 — Standard Practice for Choice of Sample Size
to Estimate the Average Quality of a Lot or Process
F 416 — Standard Test Method for Detection of
Oxidation Induced Defects in Polished Silicon Wafers
F 419 — Test Method for Determining Carrier Density
in Silicon Epitaxial Layers by Capacitance-Voltage
Measurement on Fabricated Junction of Schottky
Diodes
F 613 — Standard Test Method for Measuring
Diameter of Semiconductor Wafers
3.4 DIN Standards
3
NOTE 1: DIN Standards are available in both German and
English editions. ASTM equivalents are given in square
brackets following the title.
50431 — Measurement of the Electrical Resistivity of
Silicon or Germanium Single Crystals by Means of the
Four-Point-Probe Direct Current Method with Colinear
Four-Probe Array
50432 — Determination of the Conductivity Type of
Silicon or Germanium by Means of Rectification Test
or Hot-Probe
1 American National Standards Institute, New York Office: 11 West
42nd Street, New York, NY 10036, USA. Telephone: 212.642.4900;
Fax: 212.398.0023 Website: www.ansi.org
2 American Society for Testing and Materials, 100 Barr Harbor
Drive, West Conshohocken, Pennsylvania 19428-2959, USA.
Telephone: 610.832.9585, Fax: 610.832.9555 Website:
www.astm.org
3 Available from Deutches Institut für Normung e.V., Beuth Verlag
GmbH, Burggrafenstrasse 4-10, D-10787 Berlin, Germany, website:
www.din.de
SEMI M18-0704 © SEMI 1990, 2004 4
50433/1 — Determination of the Orientation of Single
Crystals by Means of X-Ray Diffraction
50433/2 — Determination of the Orientation of Single
Crystals by Means of Optical Reflection Figure
50433/3 — Determination of the Orientation of Single
Crystals by Means of Laue Back Scattering
50434 — Determination of Crystal Defects in
Monocrystalline Silicon Using Etching Techniques on
{111} and {100} Surfaces
50435 — Determination of the Radial Resistivity
Variation of Silicon or Germanium Slices by Means of
a Four-Point-DC-Probe
50436 — Measurement of Metallurgical Thicknes of
Epitaxial Layers of Silicon by the Stacking Fault
Method
50437 — Measuring the Thickness of Silicon Epitaxial
Layers of Silicon by Infrared Intereference Method
[F95]
50438/1 — Determination of Impurity Content in
Silicon by Infrared Absorption: Oxygen
50438/2 — Determination of Impurity Content in
Silicon by Infrared Absorption: Carbon
50439 — Determination of the Dopant Concentration
Profile of Single Crystalline Semiconductor Material by
Means of the Capacitance-Voltage Method and
Mercury Contact [F 1392, F 1393]
50438/3 — Determination of Impurity Content in
Silicon by Infrared Absorption: Boron and Phosphorus
50440/1 — Measurement of Recombination Carrier
Lifetime in Silicon Single Crystals by Means of
Photoconductive Decay Method; Measurement on Bar-
Shaped Test Samples [F28]
50441/1 — Determination of the Geometric
Dimensions of Semiconductor Slices: Measurement of
Thickness
50441/2 — Determination of the Geometric
Dimensions of Semiconductor Slices: Testing of Edge
Rounding
50441/3 — Measurement of the Geometric Dimensions
of Semiconductor Slices; Determination of Flatness
Deviation of Polished Slices by Means of Multiple
Beam Interference
50441/4 — Determination of the Geometrical
Dimensions of Semiconductor Slices: Diameter and
Flat Depth of Slices
50443/1 — Recognition of Defects and Inhomogenities
in Semiconductor Single Crystals by X-Ray
Topography: Silicon
50444 — Conversion Between Resistivity and Dopant
Density; Silicon [F723 (phosphorous and boron only)]
50445 — Contactless Determination of the Electrical
Resistivity of Semiconductor Wafers with the Eddy
Current Method
50446 — Determination of Defect Types and Defect
Densities of Silicon Epitaxial Wafers [no direct ASTM
equivalent, compare F 1726 and associated standards]
3.5 ISO Standards
4
ISO 4287/1 — Surface Roughness – Terminology –
Part 1: Surface and its Parameters
ISO 14644/1-7 — Clean Room and Associated
Controlled Environments
3.6 JEITA (formerly JEIDA) Standards
5
43 — Terminology of Silicon Wafer Flatness
53 — Test Method for Recombination Lifetime in
Silicon Wafers by Measurement of Photoconductivity
Decay by Microwave Reflectance
56 — Standard Test Method for Substitutional Atomic
Carbon Content of Silicon by Infrared Absorption
61— Standard Test Method for Interstitial Atomic
Oxygen Content of Silicon by Infrared Absorption
EM-3602 — Determining the Orientation of a
Semiconductor Silicon Single Crystal
EM-3501 — Standard Specification for Dimensional
Properties of Silicon Wafers with Specular Surface
EM-3505 — Height calibration in 1nm order for AFM
3.7 JIS Standards
6
NOTE 2: ASTM equivalents are given in square brackets
following the title.
H 0602 — Testing Method of Resistivity for Silicon
Crystals and Silicon Wafers with Four-Point Probe
H 0604 — Measurement of Minority Carrier Life Time
in Silicon by Photoconductive Decay Method [F 28]
H 0607 — Testing Methods for Conductivity Type of
Semiconductor Materials
4 International Organization for Standardization, ISO Central
Secretariat, 1, rue de Varembé, Case postale 56, CH-1211 Geneva 20,
Switzerland. Telephone: 41.22.749.01.11; Fax: 41.22.733.34.30
Website: www.iso.ch
5 Japanese Electronic and Information Technology Industries
Association, Tokyo Chamber of Commerce and Industry Bldg. 2-2,
Marunouchi 3-chome, Chiyoda-ku, Tokyo 100-0005, Japan. Website:
www.jeita.or.jp
6 Japanese Industrial Standards, Available through the Japanese
Standards Association, 1-24, Akasaka 4-Chome, Minato-ku, Tokyo
107-8440, Japan. Telephone: 81.3.3583.8005; Fax: 81.3.3586.2014
Website: www.jsa.or.jp
SEMI M18-0704 © SEMI 1990, 2004 5
H 0609 — Test Methods of Crystalline Defects in
Silicon by Preferential Etch Techniques
H 0611 — Methods of Measurement of Thickness,
Taper, and Bow of Silicon Wafers
H 0612 — Testing Method of Resistivity for Single
Crystal Silicon Wafers (with Four Point Probe) [F 84]
H 0614 — Visual Inspection for Silicon Wafers with
Specular Surfaces
Z 8741 — Method of Measurement for Specular
Glossiness
3.8 Other Standard
7
ANSI/ASME B46.1 — Surface Texture (Surface
Roughness, Waviness, and Lay)
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
4 Terminology
4.1 The items listed in the form are referenced and
defined in various documents. A reference for most
items in Parts 2 and 3 of the form is listed in Table 1.
The entries in the table are keyed to the form by item
number. Because terms related to epitaxial wafers with
buried layer are defined in this standard and because no
standardized test methods for the buried layer
parameters exist, Table 1 does not include line items
from Part 4 of the form.
4.2 General term used in this standard:
4.2.1 required (req. or req'd) — when applied to a
parameter listed in the order form, a user-supplied value
is necessary to minimally define the material for
manufacture.
4.3 Terms related to epitaxial wafers with buried
layers:
4.3.1 buried layer — a diffused region in a substrate
that is, or is intended to be, covered with an epitaxial
layer.
4.3.2 alignment precision — pattern displacement in
first mask photolithography process.
NOTE 3: Alignment precision is specified by maximum
values of X and Y, the displacement of the center of the
pattern from a reference position defined in the wafer
specification in terms of the wafer coordinate system defined
in SEMI M20, and the maximum value of θ, the angle
between the x-axis of the pattern and the primary orientation
flat (see Figure 1).
7 The Amercan Society of Mechanical Engineers, United Engineering
Center, 345 E. 47th St., New York, NY 10017.
4.3.3 pattern distortion ratio — absolute magnitude of
the quotient of the (1) difference between the width of
the pattern on the substrate and the width of the pattern
on the top surface of the epitaxial layer and (2) the
thickness of the epitaxial layer.
Figure 2
First Mask Showing Angular
Displacement
θ
Figure 3
Cross-Section View of Epitaxial Layer Showing the
Pattern Widths, a, at the Epi Surface, and b, at the
Layer-Substrate Interface
4.3.4 pattern shift ratio — lateral distance between the
center point of the pattern on the surface of the
substrate and the center point of the pattern on the
surface of the epitaxial layer divided by the epitaxial
layer thickness.
NOTE 4: Pattern shift ratio, d/t (see Figure 4), is specified in
terms of a nominal value, X, and a tolerance, ± Y, both of
which are dimensionless because both d and t are in µm.
Figure 4
Schematic Diagram Showing Line Width, A, of
Pattern on Substrate Wafer