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SEMI M47-0704 © SEMI 2001, 2004 8 silicon may be pr esent before the HF etch or be caus ed by HF etching. For this destructive measurem ent, a whole wafer or at least one quarter of a wafe r should be used. The sample is…
SEMI M47-0704 © SEMI 2001, 2004 7
8.2 Dopant Concentration
8.2.1 Secondary Ion Mass Spectroscopy (SIMS) is
utilized to determine dopant concentration in surface
silicon layer.
8.2.2 The acceptable dopant concentrations are to be
determined by agreement between users and suppliers.
8.3 Defects in Surface Silicon Layer
8.3.1 SOI Etch Pit
8.3.1.1 Defects in surface silicon layer including
stacking faults, threading dislocations and other crystal
defects are evaluated by destructive chemical etching
and microscopic etch pit density measurements. The
appropriate evaluation procedure for SOI wafers, which
depends on type of defects targeted and thickness of
surface silicon layers, is determined by agreement
between users and suppliers.
8.3.1.2 Following are examples of the evaluation on
SIMOX wafers and bonded wafers.
8.3.1.3 Example 1 — SOI etch pit evaluation in
SIMOX wafers: Samples are first immersed in HF to
remove oxide from the surface. Then the samples are
etched by Secco etch. In the case of a relatively thick
SOI layer such as 170–200 nm, freshly prepared
standard Secco Etch can be used: one part (by volume)
of a 0.15 molar solution of K
2
Cr
3
O
7
in distilled water
and two parts HF (49%). In the case of a thin SOI layer
below 100 nm, the samples are etched for 30 seconds in
the solution
5
: 50 ml of HF (49%) plus 80 ml of HNO
3
(61%) plus 160 ml of H
2
O [K
2
Cr
2
O
7
1g +
Cu(NO
3
)
2
⋅3H
2
O 4g] (a sort of diluted Secco etch). For
both cases, the etching should continue until 50 nm of
the surface Si remains. After the etching and rinsing in
water, samples are dipped in HF (49%) for 5 minutes.
The HF etches the buried oxide and creates cavities
under the etch pits. The number of etch pits is counted
through optical microscope. The etch pits include
various defects such as threading dislocations and
stacking fault pyramid.
8.3.1.4 Example 2 — SOI etch pit evaluation in bonded
SOI wafers fabricated by delamination followed by
CMP: SOI etch pit density increases when remaining
SOI thickness after Secco etching is thinner and
thinner. SOI layers thicker than 150 nm are usually
etched down to 50 nm by Secco etching before SOI
etch pits are counted. These pits are detected when
selectively etched depth or the size of defects is larger
than SOI layer thickness remaining after Secco etching.
Thus, damages deeper than 50 nm or defects larger than
50 nm can be detected. These pits come from defects
5 L. F. Giles, A. Nejim, and P. L. F. Hemment, Materials Chemistry
and Physics, vol.35, p. 129, 1993.
contained in original silicon material and/or damages or
defects induced in SOI fabrication process. The former
includes COP, bulk micro defects, oxygen precipitates,
and so on. The latter includes CMP damages, defects
induced by heat cycles and so on, as possibility. To
define origins of SOI etch pits, their distribution in
depth of SOI layers and/or that on a wafer should be
evaluated. For example, CMP damages may be
localized on surface of SOI layers. By etching SOI
surfaces up to desired depth with using non-selective
etching such as KOH followed by Secco etching, etch
pits due to CMP damages disappear. The depth
distribution of defects or damages can be evaluated in
this manner.
6
8.3.1.5 Example 3 — SOI etch pit evaluation in bonded
SOI wafers formed by epitaxial layer transfer
technology: In this case, there is no COP, bulk micro
defects, and oxygen precipitates in the SOI layer
because it is made of epitaxially grown Si on porous Si.
In addition, mechanical damage related defect is not
introduced, since the SOI surface is smoothed out by
hydrogen annealing instead of polishing. The major
defect in this type of SOI wafers is same sided
pyramidal stacking fault, that is induced at the initial
stage of the epitaxy, and is grown through the epitaxy
with upside-down pyramidal shape
7
, and then is turned
upside-down again by bonding. This defect is decorated
as the etch pit by standard or diluted Secco’s etching as
described in Example 1 in conjunction with HF
dipping. It is enough to etch until 50 nm of the SOI
layer remaining to etch the defect portion through the
SOI layer selectively by the defect etching such as
Secco etching because the stacking fault penetrates
through the SOI layer. The following HF dipping
etches the BOX through the etch pit to form large
cavity. It helps to count low density of defects in a wide
observation area with low magnification microscope.
8.3.2 Threading Dislocation
8.3.2.1 The etching of the SIMOX sample shown
above in Section 8.3.1.3 (Example 1) is terminated
when the remaining surface silicon layer thickness is
1/3–1/2 of the initial thickness and then dipped in HF as
the same manner as Example 1. In this case the etch
pits include mainly threading dislocations only which
can be counted through optical microscope.
8.3.3 HF Defect
8.3.3.1 Measurement of the microscopic etch pit
density following an HF etch is commonly used to
disclose defects in SOI material. Pitting of surface
5 K. Mitani, H. Aga, and M. Nakano, Jpn. J. Appl. Phys. vol.36, p.
1646 1997.
7 N. Sato, K. Sakaguchi, K. Yamagata, Y. Fujiyama, J. Nakayama,
and T. Yonehara, Jpn. J. Appl. Phys. vol.35, p. 973 (1996).
SEMI M47-0704 © SEMI 2001, 2004 8
silicon may be present before the HF etch or be caused
by HF etching. For this destructive measurement, a
whole wafer or at least one quarter of a wafer should be
used. The sample is placed in concentrated (49%) HF
for 10 to 15 minutes or diluted (e.g. 25%) HF for longer
time (e.g. 3 to 4 hours), then removed, rinsed and dried.
If there are pits or voids and/or metal particles or
silicides formed in the surface silicon layer, the HF
etches the metals/silicides and then etch the buried
oxide. This results in local etching of BOX with 25−50
µm diameter (depending on the HF concentration and
the etch time) centered on the original defects. The
defect density is then measured in an optical
microscope using a 5× objective and 10× eyepiece or
comparable setup. The samples should be scanned for
whole surface within edge exclusion boundary.
8.3.4 Void
8.3.4.1 Voids are determined as an unbonded area on
bonded SOI wafers. See SEMI M41. Because SOI layer
in thin bonded SOI wafers are typically 0.2 µm thick or
thinner, void areas are broken and SOI layers as well as
BOX are usually absent. By this reason, voids are
specified as local absence of SOI layers and/or BOX in
bonded wafers in this specification.
8.3.4.2 Visual inspection — Under visible light, the
edge of voids is detected because the edge area is step-
shaped due to absence of SOI layers and/or BOX
layers. See Section 8.8 for inspection conditions.
8.3.4.3 Detection as large LLS — The edge of local
absence of SOI layer and/or BOX scatters light.
Therefore, voids are detected as large LLS. See Section
8.7.2 for the principle. A size of LLS corresponding to
various sizes of voids should be calibrated or correlated
by comparison of defects one by one using a
microscope.
8.4 Surface Roughness
8.4.1 AFM (Atomic Force Microscope) — By
contacting the probe equipped with the cantilever onto
the wafer surface of the sample, and by scanning the
cantilever and detecting the variation by optical
method, the roughness information is obtained. A
tapping mode is commonly used.
8.5 Metal Contamination
8.5.1 The surface metal contamination can be
measured by TXRF, AAS and ICP-MS methods.
8.5.2 TXRF (Total X-Ray Fluorescence) — Total X-ray
Fluorescence uses a low angle incident, and a tightly
collimated X-ray beam excites the characteristic X-rays
from impurity atoms near the sample surface. Usually,
the angle of X-ray incidence is less than 0.1 degree. The
element identification and the amount of the element
can be obtained by measuring energy and intensities of
fluorescence X-ray. The instrument provides a map of
impurity element distribution. Surface roughness may
change metal detection sensitivity. Thus, calibration is
suggested before samples with deferent level of
roughness, e.g. back surface, are measured. A reference
for details is SEMI MF1526.
8.5.3 AAS (Atomic Absorption Spectroscopy)
8.5.3.1 The elemental characteristic absorption of the
atom is measured by introducing sample solution as
aerosol into the flame and then spectral absorption
through the flame from the light source is detected by
the spectrometer. The flameless method, superior to the
flame method in the sensitivity, is now broadly used.
8.5.3.2 Sample Preparation — Careful sample
preparation is necessary for the precise measurement.
SOI wafer surface is exposed to HF vapor, and metals
on the surface are collected as droplet. To improve
sensitivity, the volume of collective solution should be
as small as possible and HF drops are rolled all over the
surface in collective operation. In case of precious
metals, it is better to use other kinds of collective
solutions instead, since they are not dissolved or
collected by HF solution itself.
Examples:
1. For Cu ; HF-H
2
O
2
(HF (50 wt.%) : H
2
O
2
(31
wt.%): H
2
O = 1 : 17 : 82 volume ratio)
2. For Au and Pt ; aqua regia (HNO
3
(68 wt.%) : HCl
(36 wt.%) = 1 : 3 volume ratio)
8.5.4 ICP-MS (Inductively Coupled Plasma Mass
Spectroscopy)
8.5.4.1 ICP-MS is composed of ICP (Inductively
Coupled Plasma) part as an ion source and MS (Mass
Spectrometer) part, which measures the ions generated
at ICP part. Usually, sample solution is vaporized in the
nebulizer and then finally introduced into Argon plasma
in the silica tube called torch through the spray
chamber. The sample is decomposed, evaporated,
atomized and then ionized in the Argon plasma. Except
for few atoms that have relatively high ionization
potential, most of the elements (> 90%) can be ionized.
Ions are identified and measured in amount by the mass
spectrometer.
8.5.4.2 Sample Preparation — The same method as
AAS method is applicable. In case of quantitative
measurement of Fe, since its mass weight is close to
that of ArO
+
, it is necessary to pay attention to
degradation of detection sensitivity.
SEMI M47-0704 © SEMI 2001, 2004 9
8.6 BOX Defect
8.6.1 BOX Pinhole Measurement-1 (by CuSO
4
plating
or copper decoration)
8.6.1.1 BOX pinhole evaluations shall be made by
CuSO
4
plating or copper decoration methods. They can
be also evaluated by BOX capacitor dielectric
breakdown, the details of which are explained later in
BOX Pinhole Measurement-2.
8.6.1.2 In evaluation by CuSO
4
plating method, the
sample wafer is placed (front face down) on a paper
towel soaked in 20% CuSO
4
solution on top of a copper
plate. An aluminum plate is placed on the back of the
wafer. The copper plate is grounded, and −25 V
DC
is
applied to the aluminum plate. Small leakage currents
(sub-µA) through pinholes in the BOX cause copper to
plate out onto the towel with the density same as BOX
pinhole density.
8.6.1.3 In evaluation by copper decoration method, an
SOI layer is first etched off by KOH solution to expose
a BOX layer. Then the wafer is immersed in methanol
and brought downward into direct contact with the
gold-coated cathode. A copper mesh as an anode is
immersed in the liquid 5 mm above the wafer. Required
voltage is applied, such as the electric field in the
buried oxide layer is 1 MV/cm. The voltage is
measured at the oxide surface with a surface voltage
probe. Localized copper decorations at pinhole sites in
the oxide are observed with a low power optical
microscope.
8.6.2 BOX Capacitor Dielectric Breakdown — This
parameter can be measured with BOX capacitor. The
BOX thickness affects both the test procedure (such as
capacitor area and voltage criterion) and the allowable
values of measured parameters. These should be
determined by agreement between users and suppliers.
8.6.2.1 Test Structure — BOX capacitor utilizing
mesa-etched SOI layers and Si substrates for both
electrodes to apply electric field to the embedded buried
oxide is used. The area of capacitor, which affects the
breakdown voltage, should be determined by agreement
between users and suppliers. Typical capacitor area is
0.01–0.1 cm
2
. The electrode material and thickness
affect the breakdown phenomena due to thermal effects,
and so should be included in the agreement.
8.6.2.2 Test Method: Staircase I-V Measurement —
Voltage is stepped in one-volt increments from zero to
until destructive breakdown is sensed. The test detects
the onset of high field conduction, as well as the point
of destructive or massive charge injection and trapping.
8.6.3 BOX Pinhole Measurement-2 (by Dielectric
Breakdown)
8.6.3.1 Buried oxide pinhole can be detected also by
BOX capacitor.
8.6.3.2 Test Structure — BOX capacitor having an area
equal to or greater than 0.05 cm
2
.
8.6.3.3 Test Method: Staircase I-V — Measurement
testing can be done for both Type I and Type II defects
where Type I defects are silicon pipes traversing the
buried oxide, and Type II defects are local regions of
thin buried oxide. If Type II defect density is sought,
capacitors are subjected to a series of 30 voltage steps
of 3.3 volts, with current monitored after each step,
using a failure criterion of 1 nA.
8.6.3.4 Any capacitor displaying the failure current or
more for applied field less than 2 MV/cm is considered
defective. Defect density of either type is calculated
from the yield of good capacitors, (Y = 1 − # failed/#
tested), using Poisson statistics;
D = −1n (Y)/A,
where A is the total area of the capacitors tested.
8.7 Particle (LLS : Localized Light Scatterer)
8.7.1 Light Scattering Tomography — The particle
larger than predetermined threshold size is counted by
an automated particle counter.
8.7.2 Principle of Measurement — By scanning the
laser beam on the wafer surface, the light scattered by
particles on a wafer is detected. The scattered light and
the noise from the wafer surface is detected as a direct
current, on the other hand, the scattered light by the
particles can be detected as pulse components. The
particle size can be calibrated with standard polystyrene
latex spheres. SOI wafers usually have scattering noise
from the layer interface. It is necessary to reduce
incident angle of the laser beam to increase the
reflective component from the surface. For example,
S/N ratio is improved when using S-polarized light of
10 degree incident, 85% of its component is reflected
from silicon surface.
NOTE 2: Detailed procedure of size calibration with standard
polystyrene latex spheres: Refer to ASTM F1620.
NOTE 3: Measurement procedure should be determined by
agreement between users and suppliers.
8.8 Visual Inspection — SOI wafer can be visually
inspected in accordance with SEMI MF523. The
automatic inspection equipment is also used when
available. For visual inspection, the collimated high
intensity bright light (e.g. 500,000 lux) is used. Under
using this light, SOI wafer is inspected for haze, slip,