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SEMI M11-0704 © SEMI 1988, 2004 25 ITEM p/p - EPITAXIAL CIRCUIT WAFER (DRAM) p/p + EPITAXIAL CIRCUIT WAFER (Logic/ DRAM) p/p ++ EPIAXIAL CIRCUIT WAFER (Logic) 6.2.2 Notch Angle 90 +5, -1 degrees 90 +5, -1 degrees 90 +5, …

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SEMI M11-0704 © SEMI 1988, 2004 24
Table 7 Guide For The Specification Of 0.18 Micron Design Rule
ITEM
p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPIAXIAL
CIRCUIT WAFER
(Logic)
1.0 GENERAL CHARACTERISTICS
1.1 Growth Method Cz or MCz * Cz or MCz * Cz or MCz *
1.2 Crystal Orientation/Tolerance
{100} ± 1° {100} ± 1° {100} ± 1°
1.3 Conductivity Type
p/p
-
p/p
+
p/p
++
1.4 Dopant Boron Boron Boron
1.5 Nominal Edge Exclusion 3 mm 3 mm 3 mm
2.0 ELECTRICAL CHARACTERISTICS
2.1.1 Resistivity (Center Point)
0.8–15 Ω·cm*
(match epi layer)
0.01–0.02 Ω·cm* 0.005–0.010 Ω·cm*
2.1.2 Resistivity (Tolerance) (see row 2.1.1) (see row 2.1.1) (see row 2.1.1)
2.2 Radial Resistivity Variation (RRG) < 20% * < 20% * < 20% *
2.3 Resistivity Striations NS * (See Note 2.) NS * (See Note 2.) NS * (See Note 2.)
2.4 Minority Carrier Recombination Lifetime NS * (See Note 2.) NS * (See Note 2.) NS * (See Note 2.)
3.0 CHEMICAL CHARACTERISTICS
3.1.1 Oxygen Concentration (Nominal) user/supplier user/supplier user/supplier
3.1.2 Oxygen Concentration (Tolerance: within
shipment variation)
± 1.5 ppma * ± 2.0 ppma *
(See Note 3.)
± 2.0 ppma *
(See Note 3.)
3.2 Radial Oxygen Variation " 10% *
10 mm from Edge
" 10% *
10 mm from Edge
" 10% *
10 mm from Edge
3.3 Carbon Concentration " 0.5 ppma * See Note 3 See Note 3
4.0 STRUCTURAL CHARACTERISTICS
4.1 Dislocation Etch Pit Density NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
4.2 Slip none none none
4.3 Lineage none none none
4.4 Twin none none none
4.5 Swirl none none none
4.6 Shallow Pits none none none
4.7 Oxidation-Induced Stacking Faults (OSF) NS * (See Note 2.) NS * (See Note 2.) NS * (See Note 2.)
4.8
Oxide Precipitates (BMD) O
i
Reduction (∆O
i
)
user/supplier user/supplier user/supplier
5.0 WAFER PREPARATION CHARACTERISTICS
5.1 Wafer ID Marking Per SEMI M1 Per SEMI M1 Per SEMI M1
5.2 Front Surface Thin Film(s)
5.3 Denuded Zone user/supplier user/supplier user/supplier
5.4 Extrinsic Gettering Treatment user/supplier user/supplier user/supplier
5.5 Backseal none None or as user/
supplier agreement
None or as user/
supplier agreement
5.6 Annealing None or as user/
supplier agreement
None or as user/
supplier agreement
None or as user/
supplier agreement
6.0 MECHANICAL CHARACTERISTICS
6.1 Diameter
300 ± 0.2 mm
or
200 ± 0.2 mm
300 ± 0.2 mm
or
200 ± 0.2 mm
300 ± 0.2 mm
or
200 ± 0.2 mm
6.2 Diameter Notch Dimensions Per SEMI M1 Per SEMI M1 Per SEMI M1
6.2.1 Notch Depth 1 + 0.25,
-0.00 mm
1 + 0.25,
-0.00 mm
1 + 0.25,
-0.00 mm
SEMI M11-0704 © SEMI 1988, 2004 25
ITEM
p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPIAXIAL
CIRCUIT WAFER
(Logic)
6.2.2 Notch Angle 90 +5, -1 degrees 90 +5, -1 degrees 90 +5, -1 degrees
6.3 Notch Orientation
<110> ± 1° <110> ± 1° <110> ± 1°
6.6 Edge Profile* Per SEMI M1 Per SEMI M1 Per SEMI M1
6.6.1 Edge Surface Finish Polished * Polished * Polished *
6.7 Thickness 300 mm per SEMI
M1
300 mm per SEMI
M1
300 mm per SEMI
M1
6.7.1 Thickness Variation (9-Point TTV) NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
6.7.2 Thickness Variation (GBIR)
" 3 µm " 3 µm " 3 µm
6.10 Bow NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
6.11 Warp
(only process control data required)
" 50 µm " 50 µm for wafers
without backseal
" 100 µm for wafers
with backseal
" 50 µm for wafers
without backseal
" 100 µm for wafers
with backseal
6.12 Sori NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
6.13 Flatness/Global NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
6.14
B
Flatness/Site (See NOTE 4)
SFSR " 0.18 µm SFSR " 0.18 µm SFSR " 0.18 µm
7.0 FRONT SURFACE CHEMISTRY
7.1 Surface Metal Contamination
Sodium
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Aluminum
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
Potassium
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Chromium
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Iron
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Nickel
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Copper
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Zinc
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
Calcium
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
8.0 FRONT SURFACE CRITERIA
8.1A Scratches (macro) none none none
8.1B Scratches (micro) " 10 mm (total
length)
" 10 mm (total
length)
" 10 mm (total
length)
8.3 Localized Light Scatterers
– Only particles for epitaxial wafers
– Sizes are PSL equivalents
" 60 @ ! 0.09 µm
(300 mm)
" 27 @ ! 0.09 µm
(200 mm)
or (See NOTE 5)
" 34 @ ! 0.12 µm
(300 mm)
" 15 @ ! 0.12 µm
(200 mm)
" 60 @ ! 0.09 µm
(300 mm)
" 27 @ ! 0.09 µm
(200 mm)
or (See NOTE 5)
" 34 @ ! 0.12 µm
(300 mm)
" 15 @ ! 0.12 µm
(200 mm)
" 60 @ ! 0.09 µm
(300 mm)
" 27 @ ! 0.09 µm
(200 mm)
or (See NOTE 5)
" 34 @ ! 0.12 µm
(300 mm)
" 15 @ ! 0.12 µm
(200 mm)
8.4 Edge Chips none none none
8.5-
8.16
OTHER none none none
9.0 BACK SURFACE CRITERIA
9.1 Edge Chips none none none
SEMI M11-0704 © SEMI 1988, 2004 26
ITEM
p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPIAXIAL
CIRCUIT WAFER
(Logic)
9.2-
9.5
OTHER none none none
9.6 Roughness NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
9.7
Brightness (Gloss) 60° angle of incidence,
referenced to a mirror polished wafer. NOTE:
Double-side polish process preferred
! 80% ! 80% Applies to
wafers without
backseal only.
! 80% Applies to
wafers without
backseal only.
9.X Localized Light Scatterers (See Note 6) NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
9.YA Scratches (Macro) none none none
9.YB Scratches (Micro) " 25 mm (total
length)
" 25 mm (total
length)
" 25 mm (total
length)
11.0 ADDITIONAL EPITAXIAL LAYER CHARACTERISTICS
11.1 Conductivity Type/Structure
p/p
-
p/p
+
p/p
++
11.2 Primary Dopant Boron Boron Boron
11.3 Silicon Source Gas NS (See Note 2.) NS (See Note 2.) NS (See Note 2.)
11.4 Epitaxial Growth Method NS (See Note 2.)
(see Item 5.3)
NS (See Note 2.)
(see Item 5.3)
NS (See Note 2.)
(see Item 5.3)
11.5 Net Carrier Density Target Variation (Center of
wafer)
user/supplier user/supplier user/supplier
11.6 Net Carrier Density Variation
± 5% ± 5% with backseal
± 10% without
backseal
± 5% with backseal
± 10% without
backseal
11.7 Thickness Target Variation
± 5% ± 5% ± 5%
11.8 Thickness Variation
± 10% ± 10% ± 10%
11.9 Transition Width user/supplier user/supplier user/supplier
11.X Layer Flat Zone user/supplier user/supplier user/supplier
13.1 Stacking Faults (See Note 7) < 2 per wafer < 2 per wafer < 2 per wafer
13.2 Slip/Dislocations (See Note 8) none none none
13.5-
13.13
OTHER (see Item 13.1) (see Item 13.1) (see Item 13.1)
NOTE 1: * indicates substrate specification.
NOTE 2: NS is the abbreviation for Not Specified.
NOTE 3: Practical non-destructive metrology did not exist at the time this document was approved.
NOTE 4: The site size is 32 mm × 25 mm. Partial sites are included. The metrology was being developed at the time this document was being
balloted.
NOTE 5: These values are mathematically consistent. The 0.09 µm count limit was transformed using draft international standard: ISO/DIS
14644-1 which follows the equation: 34 counts per wafer = 60 counts per wafer /(0.12 µm/ 0.09 µm)2.
NOTE 6: The process control capability is expected to be: " 500 @ ! 0.25 µm.
NOTE 7: The lot average density is < 0.0029/cm2.
NOTE 8: Tested per SEMI MF1726; a depth < 100 nm is acceptable.