semi合集-English.pdf - 第7535页
SEMI MF1771-0304 © SEMI 2003, 2004 12 RELATED INFORMATION 2 SAMPLES AND TEST STRUCTURES NOTICE: This related in formation is not an offi cial part of SEMI MF1771. It was developed durin g the original development of the …
SEMI MF1771-0304 © SEMI 2003, 2004 11
As such, soft failure criteria may be agreed upon
between users of this test method in order to meet
individual needs of the testing. Following are examples
of commonly used criteria:
R1-4.4.1 V
crit
— The voltage associated with the noise
threshold current level.
R1-4.4.2 Vsoft fail = V at J = 100 mA/cm
2
— For
many oxides, this current level is close to hard failure,
but avoids the dispersion associated with high
resistance voltage drops at high breakdown currents.
R1-4.4.3 Vsoft fail = V at I = 1.5
µ
A — This criterion
is widely used in Japan.
3
Other values of current or
current density may be used as soft failure criteria by
agreement of the parties to the test.
SEMI MF1771-0304 © SEMI 2003, 2004 12
RELATED INFORMATION 2
SAMPLES AND TEST STRUCTURES
NOTICE: This related information is not an official part of SEMI MF1771. It was developed during the original
development of the document. This related information was approved for publication by full letter ballot on
December 4, 2004.
R2-1 Proper choice and fabrication of test structures
to be used with this test method is crucial to the success
of the testing. Because of the diverse group of intended
users, specific types of test devices or fabrication
procedures have not been stipulated. It is emphasized
that planning of any test procedure must include a
complete definition of the test structures, including
fabrication parameters such as silicon starting material,
insulator material, deposition technique, thickness,
isolation technique (planar, LOCOS, or direct moat),
electrode material, including thickness doping tech-
nique and level, sheet resistance, and sample geometry
(capacitor shape and area). All these parameters must
be included in the completed report of the experiment.
A good discussion of factors affecting the choice and
fabrication of test structures for this test may be found
in Standard 35-1.
NOTICE: SEMI makes no warranties or
representations as to the suitability of the standards set
forth herein for any particular application. The
determination of the suitability of the standard is solely
the responsibility of the user. Users are cautioned to
refer to manufacturer' s instructions, product labels,
product data sheets, and other relevant literature,
respecting any materials or equipment mentioned
herein. These standards are subject to change without
notice.
By publication of this standard, Semiconductor
Equipment and Materials International (SEMI) takes no
position respecting the validity of any patent rights or
copyrights asserted in connection with any items
mentioned in this standard. Users of this standard are
expressly advised that determination of any such patent
rights or copyrights, and the risk of infringement of
such rights are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI MF1809-0704 © SEMI 2003, 2004 1
SEMI MF1809-0704
GUIDE FOR SELECTION AND USE OF ETCHING SOLUTIONS TO
DELINEATE STRUCTURAL DEFECTS IN SILICON
This guide was technically approved by the Global Silicon Wafer Committee and is the direct responsibility
of the North American Silicon Wafer Committee. Current edition approved for publication by the North
American Regional Standards Committee on April 22, 2004. Initially available at www.semi.org May 2004;
to be published July 2004. Original edition published by ASTM International as ASTM F 1809-97. Last
previous edition SEMI MF1809-02.
1 Purpose
1.1 Structural defects formed in the bulk of a silicon
wafer during its growth or induced by electronic device
processing can affect the performance of the circuitry
fabricated on that wafer. These defects take the form of
dislocations, slip, stacking faults, shallow pits, or
precipitates.
1.2 The exposure of the various defects found on or in
a silicon wafer is often the first critical step in
evaluating wafer quality or initiating failure analysis of
an errant device structure. Etching often accomplishes
this task. This guide provides information on the
selection and application of appropriate etching
solutions.
2 Scope
2.1 This guide covers the formulation, selection, and
use of chemical solutions developed to reveal structural
defects in silicon wafers.
2.2 Sample preparation, temperature control, etching
technique, and choice of etchant are all key factors in
the successful use of an etching method. This guide
provides information for several etching solutions and
provides guidance for the user to select according to the
need. Illustrations of results obtained with these
etching solutions are provided in Figures 1–32.
2.3 This guide is intended for use with other practices
and test methods. SEMI MF1725 and SEMI MF1726
are practices for analysis of crystallographic perfection
of silicon ingots and wafers, respectively, utilizing
etching solutions found in this guide, and followed by
counting in accordance with the test method SEMI
MF1810. SEMI MF1727 defines the procedures for
oxidation of the wafer prior to etching, if that is
required to expose the defect structures of interest. JIS
H 0609 is a test method that covers the entire process of
determining crystalline defects in silicon wafers.
2.4 Both this guide and JIS H 0609 emphasize the use
of etching solutions that do not contain chromic acid,
which is biologically and ecologically very hazardous
(see Section 7.6). Because of the hazardous nature of
chrome containing etchants, the use of chromic acid
containing etchants is prohibited in some jurisdictions
located in various parts of the world.
NOTE 1: See Related Information 1 for a discussion of the
relationships between this guide and JIS H-0609.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the user of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Limitations
3.1 Complicating factors are different for each etchant.
Research the choice of etchants in advance to ensure
the method and solution are compatible with the sample
and objectives. Commonly encountered problems are:
3.1.1 Inadvertent etching through the denuded zone of
an oxidized sample delineates irrelevant bulk defects
instead of the surface oxidation induced stacking faults
(OISF) expected.
3.1.2 Accelerated etching and etching artifacts can
result from excessive solution heating during the
etching process.
3.1.3 Insufficient agitation, bubble formation or
particles in the etching solution can generate artifacts
on the silicon surface that mimic actual defects.
Insufficient agitation can alter the etching rate,
increasing or decreasing it depending upon the
formulation.
3.1.4 Any solution in which the oxidation rate is
greater than the oxide dissolution rate may form oxide
layers that slow or even quench the etching process.
The presence of these oxide layers (especially for n
+
and p
+
material) obstructs the interpretation of etched
defects. Before evaluation, remove any surface oxides.
3.1.5 The wafer surface becomes rougher with longer
etch time. This rougher surface does not prevent evalu-
ation under the microscope, but it greatly reduces the
effectiveness of visual inspection under bright light.
3.1.6 Etching solutions can generate false pits that are
not associated with defects.