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SEMI MF1771-0304 © SEMI 2003, 2004 5 7.2 Shielded Triax ial Cables — Involving g uarding to minimize the noise when measuri n g low current values. 7.3 Wafer Chuck — Electrically isolated from its case/probe platen. Whil…
SEMI MF1771-0304 © SEMI 2003, 2004 4
Figure 1
Flow Diagram for Ramp Voltage Test Method
5.1.3.2 These categories have traditionally been used
for oxides thicker than about 20 nm. For thinner films,
care must be taken in their use and in proper derivation
of the oxide field strengths as described in Section 10.2.
The break point between A mode and B mode failure in
this set of categories is different from the 3 MV/cm
given in SEMI M51.
6 Summary of Test Method
6.1 A flow diagram for the ramp voltage test is
pictured in Figure 1.
6.2 Record the test specimen ID and other test identity.
6.3 Establish the test parameters relevant to the test
system and to the test specimen.
6.4 A capacitor unit on the test specimen is selected for
test, and an optional pretest of capacitor leakage is
carried out, if desired.
6.5 If the capacitor fails this pretest, the capacitor is
recorded as a category 0 failure and a new capacitor on
the test specimen is selected for test.
6.6 Otherwise, the voltage on the capacitor is set to 0
(if no pretest was conducted) or to the voltage of use (if
a pretest was carried out).
6.7 The voltage applied to the capacitor under test is
increased linearly with time at a specified rate, with
measurements of current made at intervals that must
correspond to oxide electric field changes less than a
maximum specified value.
6.8 The voltage ramp continues until hard failure
(destructive breakdown), as defined by one of several
specified failure criteria, is sensed and stored along
with the appropriate hard failure criterion.
6.9 During the measurement cycle, soft failures
corresponding to predetermined current levels are
sensed and stored.
6.10 The measurement cycle for this capacitor is
completed when hard failure is detected or when the
upper voltage limit of the test is reached.
6.11 After the test is completed (without observing
hard failure), a post-test is performed to evaluate hard
failure by sensing current at a low voltage.
6.12 The test cycle is then repeated for the next
capacitor in the array, and this is continued until all
units in the specified group have been tested.
6.13 When testing is complete, calculations and cate-
gorizing of data is done and a report is generated.
7 Apparatus
7.1 Although the test method is independent of
equipment configuration, the use of computer-
controlled probing equipment is essential as the
measurement speed precludes manual data gathering.
What is included here shall be considered a minimum.
7.1.1 Voltage Source and Sink — That is capable of
delivering/receiving between 0 and ± 100 V in the form
of an effective ramp rate of 1.0 ± 0.1 MV/cm
–1
/s
–1
either
automatically or under computer control. If use of
other ramp rates is mutually agreed upon (see Section
9.6), it must be established that hardware is available to
perform the measurement adequately. This voltage
source/sink may consist of two source-measurement
units (SMU' s) with a common ground, or just a single
SMU with a dedicated sink. The voltage source shall
be capable of sourcing at least 100 mA of current.
SEMI MF1771-0304 © SEMI 2003, 2004 5
7.2 Shielded Triaxial Cables — Involving guarding to
minimize the noise when measuring low current values.
7.3 Wafer Chuck — Electrically isolated from its
case/probe platen. While the chuck may be connected
to the reference voltage (zero, not ground), lower
electrical noise may be obtained by connecting the
voltage ramp source to the chuck and measuring the
current through the probe connection.
7.4 Probe — To contact the gate electrode. Either a
hard needle-type probe such as tungsen carbide (which
may be a single probe or a probe card) or a mercury
probe may be used.
8 Sampling
8.1 Sampling is the responsibility of the user of this
test method. However, if testing is done as part of a
comparison or correlation, sampling shall be agreed
upon in advance by all participants.
NOTE 2: Refer to the appendix of Standard 35 for a good
discussion of sampling plan statistics.
9 Procedure
9.1 Before the measurement, record the following
information for each sample: sample identity, date,
time, operator, instrument station identity (if any),
average oxide thickness, gate area in square
centimeters, gate material, oxide type (example thermal
versus deposited), structure type, conductivity type (n
or p), bias mode (accumulation or depletion), test
temperature.
9.2 Establish the test parameters relevant to the test
system and the sample. These include the voltage ramp
rate, computed in accordance with the calculation in
Section 10.2, and the noise threshold level and in some
instances the ln J-V slope ratio for the hard failure
criterion in Section 9.9.5, both determined in
accordance with the calculation in Section 10.3.
9.3 Set the applied voltage to zero volts.
9.4 Recognizing that some information on extrinsic
defects may be lost, perform a pretest as follows. If it is
desired not to lose the information on extrinsic defects,
proceed to Section 9.5.
9.4.1 Bias the gate into accumulation at the voltage of
use. If the measured current exceeds a value equivalent
to 1.0 × 10
–5
A/cm
2
(or a current value of 10 nA if the
device area is at or below 10
–3
cm
2
), record this device
as a Category 0 failure and proceed to Section 9.11.
9.5 From the starting bias condition (zero if no pretest
was done, or the voltage of use if a pretest was used)
record voltage and current.
9.6 Begin increasing the voltage bias at a rate
equivalent to an electric field increment of 1.0 ± 0.1
MV-cm
–1
-s
–1
. Note that other ramp rates may be used
if it can be shown that it does not affect the results, or if
it is agreed upon by all parties to the test.
9.7 Record current-voltage data at an interval no more
than 0.1 s between readings, or at least once near the
end of each voltage step.
9.8 After each current reading, test to see if any of the
soft failure criteria have been met. If so, store the
appropriate value.
9.9 After each current reading, check to see if one of
the hard failure criteria has been reached.
9.9.1 Check to see if the current has increased to a
value greater than or equal to 0.98 times the compliance
limit of the voltage ramp source. If so, record the
previous voltage level as the hard failure voltage, and
set the failure category to 1. Divide the current level at
the previous measurement point by the capacitor area,
and record this value as the hard failure current density
for this unit.
9.9.2 Check to see if the current has increased by a
factor of 1000 or more from the previous reading. If so,
record the previous voltage level as the hard failure
voltage, and set the failure category to 2. Divide the
current value measured at the previous point by the
capacitor area, and record this value as the hard failure
current density.
9.9.3 Check to see if the current has increased by a
factor of 10 or more in two consecutive voltage steps.
If so, record the previous voltage level as the hard
failure voltage, and set the failure category to 3. Divide
the current value measured at the previous point by the
capacitor area, and record this value as the hard failure
current density.
9.9.4 If the current is above the noise threshold level,
check for an abrupt increase in the current by a factor of
ten. If this has occurred, record the previous voltage
level as the hard failure voltage, and set the failure
category to 4. Divide the current value measured at the
previous point by the capacitor area, and record this
value as the hard failure current density.
9.9.5 If the current is above the noise threshold level,
check for an abrupt change in the logarithmic slope of
the current density-voltage characteristic of the unit.
To minimize the chance of detecting a false reading,
use the average of the previous five (V,I) data pairs to
compute the established slope, and the current and
previous (V, I) data pairs to compute the new slope. A
change by a factor of three shall constitute a failure. If
this has occurred, record the previous voltage level as
the hard failure voltage, and set the failure category to
SEMI MF1771-0304 © SEMI 2003, 2004 6
5. Divide the current value measured at the previous
point by the capacitor area, and record this value as the
hard failure current density.
9.10 After hard failure has been detected by one of the
criteria in Section 9.9 or the upper test voltage limit has
been reached, perform a post-test using the same
criteria defined for the pretest in Section 9.4.1. This is
to be done whether a pretest was elected in Section 9.4
or not. If the unit fails the post-test conditions, modify
the failure category in some way to reflect this
observation. For example, one may change the sign of
the failure category number, or add an asterisk.
9.11 Proceed to the next device to be tested, and repeat
Sections 9.3–9.10 until all devices are tested.
10 Calculations
10.1 Current and Current Density — To calculate
current (I) from a current density (J), multiply the
current density by the area of gate contact (A) as
follows:
AJI ×= (1)
NOTE 3: Example: Given a current density (J) of 1 µA/cm
2
and a gate area (A) of 0.08 cm
2
, the current would be 80 nA.
10.1.1 Similarly, compute current density (J in A/cm
2
)
from measured current (I in A) and area (A in cm
2
)
using
A
I
J = (2)
10.2 Oxide Voltage and Electric Field Strength as a
Function of Applied Voltage — Since ramp voltage test
increments and ramp rates as well as some breakdown
voltage data analyses are specified in terms of oxide
electric field strength, it is important to consider the
conversion of applied voltages to oxide voltage and
electric field values for these two cases. Historically,
oxide electric field strength has been approximated
simply by dividing the applied voltage by the thickness
of the oxide. This approximation is in error because it
neglects the offset in the zero values of applied and
oxide voltage brought about by the work function
difference between gate electrode and silicon substrate,
and the voltages dropped across the substrate (and the
gate electrode, if it is non-metallic) when the capacitor
is strongly biased during breakdown testing. These
voltage drops are made up of two components; one
associated with band bending at the interfaces with the
oxide that establishes the high fields required for
testing, and another involving additional voltage drops
due to series resistances that become significant at very
high currents. These corrections, which together
normally range up to 1 to 2 V in magnitude, might
reasonably be neglected for samples with oxides greater
than 20-nm thick, as the correction amounted to only a
few percent of the breakdown voltage values. For
thinner oxides, these additional voltage components
must be taken into account.
10.2.1 The voltage V
app
applied across an MOS
capacitor with a given gate-substrate work function
difference Φ
ms
and oxide fixed charge Q
f
may be
expressed as follows:
gatesubms
ox
f
oxapp
VV
C
Q
VV ++
Φ+−= (3)
where:
V
ox
= voltage across the oxide, V,
C
ox
= oxide capacitance, F/cm
2
,
V
sub
= voltage across the substrate, V,
V
gate
= voltage across the gate electrode (arising
from polysilicon depletion or series
resistance, V.
10.2.2 At zero volts applied, the offset due to the work
function difference and oxide charge appears
predominantly across the oxide. For setting a voltage
ramp rate, the incremental change in V
ox
with changing
V
app
is not affected by this offset, but may be decreased
by voltage increases across the silicon substrate or the
gate electrode due to band bending and series resistance
drops. For a sample in which the applied bias voltage
polarity accumulates the substrate, and the gate
electrode is metallic or of the opposite conductivity
type from the substrate (for example, p-type silicon
substrate and n+ polysilicon gate), these effects are
appreciable only for very small and very large applied
voltages. At low bias, silicon bands bend until the
surface becomes degenerate, after which the rate of
band bending becomes very low. At high biases,
significant resistive voltage drops may develop if the
test structure design is not optimized. Over the largest
portion of the test in which neither of these effects are
large, ramp rates may be computed assuming that
voltage increments applied to the device under test
appear completely across the oxide, and ∆E
ox
, the
electric field increment across the oxide, is given as
follows:
ox
app
ox
W
V
E
∆
=∆ (4)
where:
W
ox
= oxide thickness, cm.
10.2.3 For computations of oxide field strength
associated with the various hard and soft failure criteria,