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SEMI E129-1103 © SEMI 2003 11 t = [ N / A ]/ cv elect (2) Using higher v alues of N / A in Equation 2 will increase the acceptable values of t . Accepting higher val ues of c will reduce max t . A1-2.5.5 Th e value of th…

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SEMI E129-1103 © SEMI 2003 10
Table A1-2 MM Classification Levels
Class Voltage, V
M1 < 100
M2 100–199
M3 200–399
M4 ≥ 400
Table A1-3 CDM Classification Levels
Class Voltage, V
C1 < 125
C2 125–249
C3 250–499
C4 500–999
C5 1000–1499
C6 1500–1999
C7 ≥ 2000
A1-2.4 Guide Recommendations
A1-2.4.1 At the 180-nm technology node for the year
2000, it is assumed that devices (although some may
withstand higher levels of ESD) pass testing at HBM
Class 0 (250 V × 100 pF = 25 nC), MM Class M1 (100
V × 200 pF = 20 nC), and CDM Class C3 (500 V × 10
pF device capacitance = 5.0 nC).
A1-2.4.2 This guide recommends (Table 1 in Section
12.5) 2.5–10 nC at the 180-nm node in the year 2000. It
is assumed, for this and all further recommendations,
that the device capacitance is 10 pF.
A1-2.4.3 For major technology nodes, the allowable
ESD levels have decreased approximately with the
square of the ratio of the critical dimension. The
assumption is that energy dissipation capability is
proportional to the area of the feature.
A1-2.4.4 For example, in Table A1-4 at the 90-nm
node this guide recommends approximately 25% of the
180-nm node or 1 nC, at the 50-nm node the value has
changed to 0.25 nC, and at the 25-nm node the value is
0.1 nC. Intermediate technology years have been
changed accordingly.
A1-2.5 Recommendations for Particle Deposition
A1-2.5.1 SEMI E78 Related Information 1.2.2
discusses the enhancement of particle deposition due to
electrostatic fields from charges on the wafer surface.
This section attempts to develop the guide
recommendations for minimizing particle deposition
based on that discussion.
N/A = cv
elect
t (1)
where N/A equals the particle burden added to a wafer
during exposure time t, to a particle concentration c, in
an environment characterized by an electrostatic
particle deposition velocity, v
elect
.
Table A1-4 Guide Recommendations to Prevent ESD
Damage
Year
Node
Electrostatic Discharge,
nC
2000
180 nm
2.5–10
2002
130 nm
2.0
2003
100 nm
1.5
2004
90 nm
1.0
2007
65 nm
0.5
2009
50 nm
0.25
2012
32 nm
0.125
2015
25 nm
0.1
A1-2.5.2 Target values for N/A are given in the
International Technology Roadmap for Semiconductors
(ITRS 2002 Defect Reduction chapter). These target
values vary, depending on the type of product, the
critical dimensions of the technology, the type of
process, etc. An average of random particles added per
process step is developed, and for purposes of this
discussion will represent those resulting from particle
deposition. The variables c and t are process step
dependent and may or may not be controllable.
A1-2.5.3 The only variable in Equation 1 that depends
on electrical forces is v
elect
Both the particle charge and
the electric field in the vicinity of the wafer affect the
magnitude of v
elect
Particle charge is generally unknown
unless it is deliberately controlled by a neutralizing
action, and in the absence of this condition, a Fuchs-
type charge distribution is a reasonable assumption for
the particle charge. This assumption was used to
calculate the value of E
0
, the electric field at which v
elect
is equal to the particle deposition velocity from
diffusion (dominant for small particles).
A1-2.5.4 Using the process step values of c and t, and
the value of v
elect
calculated from Equation 10 in SEMI
E78 Related Information 1.2.2, the value of N/A for any
process step can be estimated. Alternatively, having
target values for N/A and c, and estimating the value of
v
elect
as outlined in the previous paragraph, allows one
to calculate the tolerable value of t:
SEMI E129-1103 © SEMI 2003 11
t = [N/A]/cv
elect
(2)
Using higher values of N/A in Equation 2 will increase
the acceptable values of t. Accepting higher values of c
will reduce max t.
A1-2.5.5 The value of the electrostatic field is initially
calculated at a distance of one wafer radius from the
wafer. While electrostatic field measurements can
certainly be made at this distance, they are typically
made at 2.5 cm (1 inch) with common instrumentation.
This is described in SEMI E43. Measurements made at
this smaller distance will be proportionally higher, but
under varying measurement conditions, it is difficult to
determine a precise relationship between electric field
and measurement distance. To provide a safety factor,
assume a linear relationship, rather than one
proportional to the square of the distance. For example,
with a 300-mm wafer, 3000 V/cm at 2.5 cm would
result in 500 V/cm at 15 cm.
A1-2.5.6 In SEMI E78, calculations were based on a
defect density N/A = 0.016 defects/cm
2
and a deposition
velocity v
elect
of 0.0105 cm/s. An example of the
resulting calculations is found in SEMI E78 Appendix 1
Table A1-2.2, a portion of which is shown in Table A1-
5.
Table A1-5 SEMI E78 Guide Table A1 – 2.2
E,
V/cm at
2.5 cm
N/A,
defects/
cm
2
v
elect
,
cm/s
ct,
s/cm
3
max t in
Class 1,
s
200 0.016 0.0105 1.524 1220
A1-2.5.7 Tables A1-6 and A1-7 below are derived
from Table A1-5 above, which is taken from SEMI E78
Appendix A1-2.2.2. They contain the same
assumptions used for the SEMI E78 table, but reflect
values for defect density (N/A) and particle deposition
velocity contained in the ITRS 2002 document for each
technology node. Assumptions are:
• Calculations are made for ISO Class 3 (formerly
Federal Standard 209E Class 1) where c ≤ 0.00124
particles/cm
3
.
• As contained in both the 1999 and 2002 ITRS,
particle deposition velocity is assumed to be 0.01
cm/s (2002 ITRS Yield Enhancement Chapter,
Notes Table 95a). Calculations are made assuming
the electrostatic deposition velocity, v
elect
, is equal
to this value.
• For N/A = 0.0141 defects/cm
2
as specified in the
1999 ITRS for the 180-nm node (Defect Reduction
Chapter, Table 77, assuming “Random Defects”
per mask layer are all the result of particle
deposition), the corresponding table becomes:
Table A1-6 Modified SEMI E78 Guide Table A1 – 2.2
E,
V/cm at
2.5 cm
N/A,
defects/
cm
2
v
elect
,
cm/s
ct,
s/cm
3
max t in
Class 1,
s
190 0.0141 0.01 1.41 1140
• The values from the 2002 ITRS (Yield
Enhancement Chapter, Table 91) N/A = 0.0093
defects/cm
2
as specified for the 130-nm node,
0.0089 defects/cm
2
for the 100-nm node, 0.0059
for the 65-nm node, 0.0056 for the 45-nm node,
0.0043 for the 32-nm node, and 0.0044 for the 22-
nm node technology are used.
• Calculations are normalized for an exposure time
of 1200 s (i.e., E values multiplied by 1140/1200).
• Relationship of electrostatic field, technology node,
and constant airborne particle concentration are
shown in Table A1-7.
• The years and technology nodes shown in Table
A1-7 correspond to those to be used in the 2003
ITRS.
A1-2.6 Recommendations for Induced ESD Damage
A1-2.6.1 The presence of electrostatic fields in
semiconductor manufacturing areas also creates the
potential for induced ESD damage. When an isolated
conductor is placed in an electric field, a charge
separation occurs in the conductor. If the conductor
momentarily touches ground, a flow of charge will
occur to the conductor. This flow of charge is a
potentially damaging ESD event. If the conductor, now
possessing excess charge, is removed from the electric
field, a second ESD event can occur when the
conductor contacts ground again.
A1-2.6.2 The most obvious example of these
phenomena occurs once the semiconductor device is
packaged. The package material is epoxy, an easily
charged insulator. The electric field from the charged
package induces a charge on the device leads. ESD
events occur when the leads contact ground during
processing.
SEMI E129-1103 © SEMI 2003 12
Table A1-7 Electrostatic Field Levels – Limit Particle
Deposition in a Class 1 Environment
Year
Node
N/A,
defects/cm
2
Electrostatic Field, V/cm
2000
180 nm
0.0141 180
2002
130 nm
0.0093 120
2003
100 nm
(2004)
(90 nm)
0.0089 114
2007
65 nm
0.0059 75
2009
50 nm
(2010)
(45 nm)
0.0056 71
2012
32 nm
0.0043 55
2015
25 nm
(22 nm)
0.0044 56
A1-2.6.3 A second problem for semiconductor
manufacturing occurs in the presence of a changing
electric field. This occurs when there is movement of
isolated conductors within an electric field, or the field
itself changes in magnitude. The result is that the
charge, and hence the voltage, induced on the
individual isolated conductors will not always be the
same, creating a potential difference between the
conductors. Under the right circumstances, ESD events
can occur between conductors at different potentials.
With the electric field changing, there is also the
likelihood that multiple ESD events will occur.
A1-2.6.4 This phenomenon of charge induced by
changing electric fields is mostly a concern in the
handling of photomasks with µm and sub-micron
feature sizes. While ESD damage occurred with 5×
photomasks with 3 to 5-µm features, it was infrequent.
At the 180-nm technology node, even 5× masks have
sub-micron features and the trend is to 4× masks,
making the feature sizes even smaller.
A1-2.6.5 The problem occurs because a photomask is
basically a large collection of closely spaced, isolated
conductors on an insulating quartz substrate. The
substrate is easily charged, creating an electric field.
The field changes whenever the spacing between the
photomask and ground changes (e.g., during handling
by robotics). Transporting the photomask, whether in
static dissipative reticle carriers or not, exposes it to
changing electric fields from other charged objects
(e.g., equipment panels, windows, work surfaces, and
equipment parts). The result is an increasing incidence
of ESD damaged photomasks as geometries shrink.
A1-2.6.6 While there have been several studies
documenting the existence of the field charging
problem on photomasks, there is currently a need for
further research to demonstrate the level at which it
occurs for production facilities. A recent study
(Montoya, et al.) was able to produce the following
information:
1. Testing was done on a photomask test device with
1.5-µm gaps between features. Approximately 800
V/cm (2 kV/inch) of electric field was needed to
cause damage.
2. Current production 180-nm photomasks are 4×
with a nominal gap width of 0.72 µm (or less
depending on the technology). ESD should occur
at 400 V/cm (1 kV/inch) or less.
3. To avoid ESD on 180-nm photomasks, electric
fields should be kept below 50% of the damage
threshold, or 200 V/cm (500 V/inch).
A1-2.6.7 Table A1-8 below is based on these
measurements. It is acknowledged that discharge
phenomena may change at very small conductor
spacing, and that the relationship to electric field may
not be a linear function of the geometry. The values in
Table A1-8 may need to be changed as more
information becomes available.
Table A1-8 Electrostatic Field Levels – Limit Induced
ESD Damage on Photomasks
Year
Node
Electrostatic Field
Limits
Induced ESD Damage,
V/cm
Electrostatic Field
Limits
Particle Attraction,
V/cm
2000
180 nm
200 (200) 180
2002
130 nm
144 (150) 120
2003
100 nm
111 (125) 114
2004
90 nm
100 (100) 114
2007
65 nm
72 (70) 75
2009
50 nm
(45 nm)
55 (50) 71
2012
32 nm
35 (35) 55
2015
25 nm
(22 nm)
27 (25) 56