semi合集-English.pdf - 第4972页

SEMI M11-0704 © SEMI 1988, 2004 29 ITEM p/p - EPITAXIAL CIRCUIT WAFER (DRAM) p/p + EPITAXIAL CIRCUIT WAFER (Logic/ DRAM) p/p ++ EPITAXIAL CIRCUIT WAFER (Logic) 5.4 Extrinsic Gettering Treatment us er/supplier user/suppli…

100%1 / 7923
SEMI M11-0704 © SEMI 1988, 2004 28
CUSTOMER PART NUMBER: REVISION DATE:
14.2 Back Seal [ ] Silicon Oxide: 5000 ± 1000 Angstroms,
[ ] Polysilicon: 10,000 ± 2000 Angstroms,
[ ] Backside Damage,
[ ] None,
[ ] Combination of: 3000 ± 1000 Angstroms
Silicon Oxide on top of 8000 ± 2000
Angstroms Polysilicon
Table 9 Guide For The Specification Of 0.13 Micron Design Rule Silicon Epitaxial Wafers
ITEM p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPITAXIAL
CIRCUIT WAFER
(Logic)
1.0 GENERAL CHARACTERISTICS
1.1 Growth Method Cz or MCz * Cz or MCz * Cz or MCz *
1.2 Crystal Orientation {100} {100} {100}
1.3 Crystal Orientation/Tolerance ± 1° ± 1° ± 1°
1.4 Conductivity type p/p- p/p+ p/p++
1.5 Dopant Boron Boron Boron
1.6 Nominal Edge Exclusion 3 mm 3 mm 3 mm
2.0 ELECTRICAL CHARACTERISTICS
2.1.1 Resistivity (Center Point) 0.8–15 $·cm * 0.01–0.02 $·cm * 0.005–0.010 $·cm *
2.2 Radial Resistivity Variation
(See Note 9.)
< 20% * < 20% * < 20% *
2.3 Resistivity Striations NS * NS * NS *
3.0 CHEMICAL CHARACTERISTICS
3.1.1 Nominal Oxygen Concentration (Center) user/supplier user/supplier user/supplier
3.1.2 Oxygen Concentration Tolerance
Per old ASTM calibration factor (See
SEMI M44.)
± 2.0 ppma *
± 2.0 ppma *
(See Note 3.)
± 2.0 ppma *
(See Note 3.)
3.2 Radial Oxygen Variation
Per SEMI MF951
" 10% *
10 mm from Edge
" 10% *
10 mm from Edge
(See Note 3.)
" 10% *
10 mm from Edge
(See Note 3.)
3.3 Carbon Concentration
(See Note 9.)
" 0.5 ppma * " 0.5 ppma
(See Note 3.) *
" 0.5 ppma
(See Note 3.) *
4.0 STRUCTURAL CHARACTERISTICS
4.1 Dislocation Etch Pit Density NS NS NS
4.2 Slip none none none
4.3 Lineage none none none
4.4 Twin none none none
4.5 Swirl none none none
4.6 Shallow pits none none none
4.7 Oxidation-Induced Stacking Faults (OSF) NS * NS * NS *
4.8 Oxide Precipitates (BMD) O
i
Reduction
(%O
i
)
user/supplier user/supplier user/supplier
5.0 WAFER PREPARATION CHARACTERISTICS
5.1 Wafer ID Marking per M1 per M1 per M1
5.2 Front Surface Thin Film(s) NS NS NS
5.3 Denuded Zone user/supplier user/supplier user/supplier
SEMI M11-0704 © SEMI 1988, 2004 29
ITEM p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPITAXIAL
CIRCUIT WAFER
(Logic)
5.4 Extrinsic Gettering Treatment user/supplier user/supplier user/supplier
5.5 Backseal none None or as
user/supplier
agreement
None or as
user/supplier
agreement
5.6 Annealing None or as
user/supplier
agreement
None or as
user/supplier
agreement
None or as
user/supplier
agreement
6.0 MECHANICAL CHARACTERISTICS
6.1 Diameter 300 ± 0.2 mm
or
200 ± 0.2 mm
300 ± 0.2 mm
or
200 ± 0.2 mm
300 ± 0.2 mm
or
200 ± 0.2 mm
6.2 Diameter Notch Dimensions
6.2.1 Notch Depth 1 +0.25,-0.00 mm 1 +0.25,-0.00 mm 1 +0.25,-0.00 mm
6.2.2 Notch Angle 90 +5,-1 degrees 90 +5,-1 degrees 90 +5,-1 degrees
6.3 Notch Orientation <110> ± 1° <110> ± 1° <110> ± 1°
6.61 Edge Profile* per SEMI M1 per SEMI M1 per SEMI M1
6.6.2 Edge Surface Finish Polished * Polished * Polished *
6.7 Thickness 775 ± 25 µm*
[300 mm diameter]
or
725 ± 20 µm*
[200 mm diameter]
775 ± 25 µm*
[300 mm diameter]
or
725 ± 20 µm*
[200 mm diameter]
775 ± 25 µm*
[300 mm diameter]
or
725 ± 20 µm*
[200 mm diameter]
6.7.1 Thickness Variation (9-Point TTV) NS NS NS
6.72 Thickness Variation (GBIR) " 3 µm " 3 µm " 3 µm
6.9 Surface Orientation 100 100 100
6.10 Bow NS NS NS
6.11 Warp
(only process control data required)
" 50 µm " 50 µm for wafers
without backseal
" 100 µm for wafers
with backseal
" 50 µm for wafers
without backseal
" 100 µm for wafers
with backseal
6.12 Sori NS NS NS
6.13 Flatness/Global NS NS NS
6.14B Flatness/Site (See Note 4) SFSR " 0.13 µm SFSR " 0.13 µm SFSR " 0.13 µm
7.0 FRONT SURFACE CHEMISTRY
7.1 Surface Metal Contamination
See Note 9
Sodium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Aluminum " 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
Potassium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Chromium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Iron " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Nickel " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Copper " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Zinc " 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
Calcium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
8.0 FRONT SURFACE CRITERIA
8.1A Scratches (macro) none none none
8.1B Scratches (micro) " 10 mm (total length) " 10 mm (total length) " 10 mm (total length)
SEMI M11-0704 © SEMI 1988, 2004 30
ITEM p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPITAXIAL
CIRCUIT WAFER
(Logic)
8.3 Localized Light Scatterers
- Only particles for epitaxial wafers
- Sizes are PSL equivalents
300 mm:
" 200 @ ! 0.09 µm
or
" 112 @ ! 0.12 µm
(See note 5.)
300 mm:
" 200 @ ! 0.09 µm
or
" 112 @ ! 0.12 µm
(See note 5.)
300 mm:
" 200 @ ! 0.09 µm
or
" 112 @ ! 0.12 µm
(See note 5.)
200 mm:
" 89 @ ! 0.09 µm
or
" 50 @ ! 0.12 µm
(See note 5.)
200 mm:
" 89 @ ! 0.09 µm
or
" 50 @ ! 0.12 µm
(See note 5.)
200 mm:
" 89 @ ! 0.09 µm
or
" 50 @ ! 0.12 µm
(See note 5.)
8.4 Edge Chips none none none
8.5-8.16 OTHER none none none
9.0 BACK SURFACE CRITERIA
9.1 Edge Chips none none none
9.2-9.5 OTHER none none none
9.6 Roughness NS NS NS
9.7 Brightness (Gloss) 60° angle of incidence,
referenced to a mirror polished wafer.
NOTE: Double-side polish process
preferred
! 80%. ! 80% Applies to
wafers without
backseal only.
! 80% Applies to
wafers without
backseal only.
TBD Localized Light Scatterers (See Note 6.) NS NS NS
TBD Scratches (Macro) none none none
TBD Scratches (Micro) Cumulative Length
" 10% of the Wafer
Diameter
Cumulative Length
" 10% of the Wafer
Diameter
Cumulative Length
" 10% of the Wafer
Diameter
11.0 ADDITIONAL EPITAXIAL LAYER CHARACTERISTICS
11.1 Conductivity Type/Structure p/p- p/p+ p/p++
11.2 Primary Dopant Boron Boron Boron
11.3 Silicon Source Gas NS NS NS
11.4 Epi Growth Method NS
(see item 5.3)
NS
(see item 5.3)
NS
(see item 5.3)
11.5 Carrier Density Range - Must be met at all
points on the wafer surface inside the edge
exclusion (See Note 11.)
User/supplier
agreement
User/supplier
agreement
User/supplier
agreement
11.6 Layer Thickness (Target Value at Wafer
Center and Tolerance)
Target: user/supplier
agreement
Tolerance: ± 5%
Target: user/supplier
agreement
Tolerance: ± 5%
Target: user/supplier
agreement
Tolerance: ± 5%
11.7 Thickness Variation (within wafer per
SEMI M11)
10% 10% 10%
11.8 Transition Width User/supplier
agreement
User/supplier
agreement
User/supplier
agreement
11.9 Layer Flat Zone User/supplier
agreement
User/supplier
agreement
User/supplier
agreement
13.1 Stacking Faults (See Note 7.) < 0.012/cm
2
< 0.012/cm
2
< 0.012/cm
2
TBD Large Area Defects (LAD’s)
(See Note 7.)
< 0.006/cm
2
< 0.006/cm
2
< 0.006/cm
2
13.2 Slip/Dislocations (See Note 8.) none none none
13.5 -
13.13
OTHER (see 13.1) (see 13.1) (see 13.1)