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SEMI M9-0999 © SEMI 1986, 1999 1 SEMI M9-0999 SPECIFICA TIONS FOR POLISHED MONOCRYSTA LLINE G A LLIUM ARSENIDE SLICES NOTE: This speci fication was mod ified in Sep tember 1999 to co rrect an editorial erro r present in …

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SEMI M8-0703 © SEMI 1984, 2003 12
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consent of SEMI.
SEMI M9-0999 © SEMI 1986, 19991
SEMI M9-0999
SPECIFICATIONS FOR POLISHED MONOCRYSTALLINE GALLIUM
ARSENIDE SLICES
NOTE: This specification was modified in September 1999 to correct an editorial error present in Figure 4A.
A Publication Improvement Proposal (PIP) form was submitted in August 1999.
1 Preface
1.1 These specifications cover two groups of substrate
requirements for monocrystalline high-purity gallium
arsenide wafers used in semiconductor and electronic
device manufacture. Dimensional and crystallographic
orientation characteristics and limits on surface defects
are the only standardized properties set forth below.
1.2 A complete purchase specification may require
that additional physical, electrical, and bulk properties
be defined. These properties are listed, together with
test methods suitable for determining their magnitude
where such procedures are documented.
1.3 These specifications are directed specifically to
gallium arsenide wafers with one or both sides
polished. Unpolished wafers or wafers with epitaxial
films are not covered; however, purchasers of such
wafers may find these specifications helpful in defining
their requirements.
1.4 The material is Single Crystal Gallium Arsenide
(GaAs) having a cubic zinc blende structure and having
the following properties. The following properties are
for use as guidelines:
Density 5.316 gm/cm
3
Melting Point
1238°C
Dielectric Constant 13.1
Lattice Parameter 5.654 Å
Energy Gap 1.42 eV
1.5 For reference purposes, SI (System International,
commonly called metric) units shall be used.
2 Applicable Documents
2.1 ASTM Standards
1
E 122 Practice for Choice of Sample Size to
Estimate Average Quality of a Lot or Process
F 26 Test Methods for Determining the Orientation
of a Semiconductive Single Crystal
1 American Society for Testing and Materials, 100 Barr Harbor
Drive, West Conshohoken, PA 19428-2959 (All cited standards
except for E 122 may be found in Volume 10.05 of the Annual Book of
ASTM Standards; E 122 may be found in Volume 14.02.)
F 76 Test Methods for Measuring Hall Mobility and
Hall Coefficient in Extrinsic Semiconductor Single
Crystals
F 154 Practices and Nomenclature for Identification
of Structures and Contaminants Seen on Specular
Silicon Surfaces
F 523 Practice for Unaided Visual Inspection of
Polished Silicon Slices
F 533 Test Method for Thickness and Thickness
Variation of Silicon Slices
F 534 Test Method for Bow of Silicon Slices
F 613 Test Method for Measuring Diameter of
Silicon Slices and Wafers
F 657 Test Method for Measuring Warp and Total
Thickness Variation on Silicon Slices and Wafers by a
Non-Contact Scanning Method
F 671 Test Method for Measuring Fiducial Flat
Length and Deviation
F 928 Test Method for Edge Contour of Silicon
Wafers
2.2 Other Standard
2
ANSI/ASQC Z1.4-1993 Sampling Procedures and
Tables for Inspection by Attributes
3 Definitions
3.1 Bow of a semiconductor slice or wafer, a
measure of concave or convex deformation of the
median surface of a slice or wafer, independent of any
thickness variation which may be present. Bow is a
bulk property of the test specimen, not a property of an
exposed surface. Generally, bow is determined with a
test specimen in a free, unclamped condition. Units of
bow are generally micrometers or inches.
3.2 Dopant a chemical element, usually from the
second, fourth, or sixth columns of the periodic table
for the case of III-V compounds, incorporated in trace
amounts in a semiconductor crystal to establish its
conductivity type and resistivity.
2 American Society for Quality Control, 611 East Wisconsin Avenue,
Milwaukee, WI 53202
SEMI M9-0999 © SEMI 1986, 1999 2
3.3 Lot for the purpose of this document, (a) all of
the wafers of nominally identical size and
characteristics contained in a single shipment, or (b)
subdivisions of large shipments consisting of wafers as
above which have been identified by the supplier as
constituting a lot.
3.4 Flat Diameter the linear dimension across the
surface of a semiconductor wafer from the center of the
flat through the wafer center to the circumference of the
wafer on the opposite edge along the diameter
perpendicular to the flat. (See Figure 6.)
NOTE 4 The flat diameter may be associated with
the primary orientation flat, with a secondary flat, if
present, or with any other flat, if present. In such cases,
the terms may be modified as primary orientation flat
diameter, secondary flat diameter, etc.
3.5 Orthogonal Misorientation in { 100} wafers cut
intentionally “off-orientation,” the angle between the
projection of the vector normal to the slice surface onto
the { 100} plane and the projection on that plane of the
nearest direction. (See Figure 5.)
3.6 Total Thickness Variation (TTV) the difference
between the maximum and minimum thickness values
of a slice or wafer encountered during a scan pattern or
a series of point requirements. TTV is generally
expressed in micrometers or mils (thousandths of an
inch).
3.7 Warp of a semiconductor slice or wafer, the
difference between the maximum and minimum
distances of the median surface of the slice or wafer
from a reference plane, encountered during a scan
pattern. Warp is a bulk property of the test specimen,
not a property of an exposed surface. Warp is generally
expressed in micrometers or mils (thousandths of an
inch).
3.8 Edge Contouring on slices whose edges have
been shaped by mechanical and/or chemical means, a
description of the profile of the boundary of the slice
joining the front and back sides.
4 Ordering Information
4.1 Purchase orders for gallium arsenide wafers
furnished to this specification shall include the
following items:
4.1.1 Nominal diameter (see applicable SEMI
Standard for polished GaAs wafers),
4.1.2 Thickness (see applicable SEMl Standard for
polished GaAs wafers),
4.1.3 Total Thickness Variation (see applicable SEMI
Standard for polished GaAs wafers),
4.1.4 Surface orientation (see applicable SEMI
Standard for polished GaAs wafers). There are two
options of flat location for 2" and 3" diameter polished
mono-crystalline GaAs wafers for integrated circuit and
optoelectronic applications. They are V-Groove (as
illustrated in Figures 1 and 3) and Dove-Tail (as
illustrated in Figures 2 and 4). These designations
describe the shape of groove that can be etched
perpendicular to the primary flat.
The following are the options of wafer surface
orientation:
A. (100) ± 0.5° as shown in Figures 1 and 2
B. For V-Groove option:
(100) off 2° toward the (110) plane which is located
between the primary and secondary flats as shown in
Figure 3. Figure 5 illustrates orthogonal misorientation.
For Dove-Tail option:
(100) off 2° toward any of the nearest (110) planes as
shown in Figure 4. Figure 5 illustrates orthogonal
misorientation.
4.1.5 Lot Acceptance Procedures (see Section 8),
4.1.6 Certification (see Section 11),
4.1.7 Packing and Marking (see Section 12).
4.2 Optional Criteria The follo wing items may be
specified optionally in addition to those listed above:
4.2.1 Crystal Growth Method,
4.2.2 Etch Pit Density (EPD) of Crystal,
4.2.3 Crystal Growth Perfection,
4.2.4 Impurity Type,
4.2.5 Surface Condition of Wafer,
4.2.6 Edge Contour,
4.2.7 Mobility,
4.2.8 Resistivity,
4.2.9 Carrier Concentration,
4.2.10 Thermal Conversion Characteristics.
5 Dimensions and Permissi ble Variations
5.1 The material shall conform to the dimensions and
dimensional tolerances as specified in the applicable
polished gallium arsenide slice standard.
5.2 If edge contoured wafers are specified on the
purchase order, the profile shall conform to the
following requirements at all points on the wafer
periphery.