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SEMI M1-0305 © SEMI 1978, 2005 50 REVISION RECORD NOTICE : The Revision Record is an official part of the sta nda rd. It is optional and placed at the end of the standard. Ne gative votes may not be based on the Revision…

SEMI M1-0305 © SEMI 1978, 2005 49

R2-9.2 X-ray Topography (DIN 50443/1) can also be used to test for defects in silicon wafers. This method may

see defects that do not intersect the surface, and can also be used to examine for bulk defects in the wafer (see

Section 2.4.10 of Table 1).

R2-9.3 Automated Surface Inspection by Light Scattering can also be used to detect many surface defects,

especially on polished surfaces. These techniques have not been fully standardized but there is a group of standards

that assist in making certain that the instruments are performing correctly. These include SEMI M52 for

determining if surface scanning inspection systems (SSIS) have suitable characteristics for the desired use, SEMI

M53 for calibrating SSISs, SEMI M58 for assuring that the calibration artifacts meet the desired requirements,

SEMI M50 for determining capture rate characteristics of SSISs and SEMI M35 for discriminating among various

surface features with an SSIS. Because of the lack of complete standardization, the testing conditions for use of

SSISs should be agreed upon between supplier and customer.

R2-9.3.1 Localized Light Scatterers — SSISs are particularly appropriate for inspecting polished surfaces for the

presence of particles and other localized light scatterers (LLS). In this case, it is essential to define the size ranges

(in units of latex sphere equivalents, LSE) as well as the maximum permissible counts, usually in terms of counts

per wafer, but occasionally in terms of counts per unit area.

R2-9.4 Surface Roughness affects the size of particle or other LLS that can be detected on a surface. SEMI M40

provides guidance on how to measure and report surface roughness on planar surfaces. Surface microroughness can

be determined with SSISs, through the use of the power spectral density as described in SEMI MF1811, or with an

atomic force microscope, which can be calibrated with the use of JEITA EM-3505. Other documents useful in

connection with surface microroughness measurements include ISO 4287/1 and ANSI/ASME B46.1. Because of

the lack of standardization, the testing conditions for surface microroughness measurements should be agreed upon

between supplier and customer.

R2-9.5 Back Surface Finish of 300 mm diameter wafers is specified as “polished.” The standard quantitative test

for the polish finish, which is not a smooth as the mirror polished front surface, is gloss. The general techniques for

determining gloss are given in ASTM Test Method D 523 and JIS Z 8741. However, for measuring gloss of silicon

surfaces, visible illumination at a 60 angle of incidence is referenced to a mirror polished silicon front surface.

Surface microroughness measurements (see ¶R2-9.4) can also be used as a quantitative test for back surface finish,

especially when it is necessary to observe particles or other LLSs smaller than 0.25 m LSE on the surface.

NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any

particular application. The determination of the suitability of the standard is solely the responsibility of the user.

Users are cautioned to refer to manufacturer's instructions, product labels, product data sheets, and other relevant

literature, respecting any materials or equipment mentioned herein. These standards are subject to change without

notice.

By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position

respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this

standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and

the risk of infringement of such rights are entirely their own responsibility.

SEMI M1-0305 © SEMI 1978, 2005 50

REVISION RECORD

NOTICE: The Revision Record is an official part of the standard. It is optional and placed at the end of the

standard. Negative votes may not be based on the Revision Record.

Cycle Ballot Section Description Committee

Approval

0305 3907 Entire

Document

This revision combines most of SEMI M1 with parts of SEMI M18 to

form a new set of specifications that includes:

Purpose, a new scope, referenced standards, ordering information

(consolidated with some of SEMI M18), requirements (assembled

from several existing sections in SEMI M1), sampling, test methods,

certification, and packing and shipping container labeling sections;

Basic polished wafer specifications (developed by the Basic Wafer

Specification TF);

The two appendices and one related information section included in

previous editions of SEMI M1; and

A new related information section on detailed discussion of test

methods, based largely on material previously in SEMI M28.

A new table of contents has been added to make it easier to locate

specific information in the standard, and the terminology section of

SEMI M1 was combined with SEMI MF1241 and issued as SEMI

M59. The EDI codes from SEMI M18 remain in that standard.

The material in all of the substandards previously included at the end of

SEMI M1 is now included in the body of the document with no change

of the technical content. In addition, polished wafers and substrates

have been assigned category numbers based on the previous

substandard designation number. In some cases there are two

categories, based on differences in the edge rounding template used.

All of the specification requirements previously in the substandards

have been moved to tables as follows:

Substandard Nominal Diameter Located in Table Wafer Category(s)

SEMI M1.1 2 inch 4 1.1

SEMI M1.2 3 inch 4 1.2

SEMI M1.5 100 mm 5 1.5

SEMI M1.6 100 mm 5 1.6

SEMI M1.7 125 mm 5 1.7

SEMI M1.8 150 mm 6 1.8.1 and 1.8.2

SEMI M1.9 200 mm 9 1.9.1 and 1.9.2

SEMI M1.10 200 mm 8 1.10.1 and 1.10.2

SEMI M1.11 100 mm 7 1.11

SEMI M1.12 125 mm 7 1.12

SEMI M1.13 150 mm 8 1.13.1 and 1.13.2

SEMI M1.15 300 mm 9 1.15

Additional material related to 300 mm wafers is given elsewhere in

SEMI M1, most notably in ¶6.5.1.4, which describes the wafer marking

requirements. Also it should be noted that (1) the information on

surface orientation, for which the substandards allowed any of a

number of options, has been moved to Item 2-1.8 of Table 1, Silicon

Wafer Specification Format for Order Entry, Parts 1 and 2, and (2) the

information on orthogonal misorientation, which is the same for all

(111) silicon wafers has been moved to Item 2-1.9 of the same table.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction of

the contents in whole or in part is forbidden without express written

consent of SEMI.

SEMI M2-1103 © SEMI 1985, 2003 1

SEMI M2-1103

SPECIFICATlON FOR SILICON EPITAXIAL WAFERS FOR DISCRETE

DEVICE APPLICATIONS

This specification was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the North American Silicon Wafer Committee. Current edition approved by the North

American Regional Standards Committee on July 12, 2003. Initially available at www.semi.org October

2003; to be published November 2003. Originally published in 1985; previously published September 1997.

1 Purpose

1.1 This specification defines silicon epitaxial wafer

requirements for discrete semiconductor device

manufacture. It is restricted to wafers with device

feature sizes in excess of 1 µm or wafers with epi layers

thicker than 25 µm. By defining inspection procedures

and acceptance criteria, suppliers and consumers may

uniformly define product characteristics and quality

requirements.

2 Scope

2.1 This specification covers characteristics of both the

substrate (through reference to SEMI M1) and the

epitaxial layer including handling and packaging.

2.2 This specification is specifically directed to silicon

homoepitaxial deposits thicker than 25 µm on

homogeneous silicon substrates or similar epitaxial

wafers that are to be used to make discrete devices.

Specifications for silicon epitaxial wafers with greater

uniformity and more stringent surface defect criteria are

given in SEMI M11

2.3 The primary standardized properties set forth in

this specification relate to physical, electrical, and

surface defect parameters.

2.4 A complete purchase specification requires that

additional physical properties be specified along with

suitable test methods for their measurement. SEMI

M18 may be used for this purpose.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M1 — Specifications for Polished

Monocrystalline Silicon Wafers

SEMI M11 — Specifications for Silicon Epitaxial

Wafers for Integrated Circuit (IC) Applications

SEMI M17 — Specification for a Universal Wafer Grid

SEMI M18 — Format for Silicon Wafer Specification

Form for Order Entry

SEMI MF95 — Test Method for Thickness of Epitaxial

Layers of Silicon on Substrates of the Same Type by

Infrared Reflectance

SEMI MF110 — Test Method for Thickness of

Epitaxial or Diffused Layers in Silicon by the Angle

Lapping and Staining Technique

SEMI MF154 — Guide for Identification of Structures

and Contaminants Seen on Specular Silicon Surfaces

SEMI MF374 — Test Method for Sheet Resistance of

Silicon Epitaxial, Diffused, and Ion-Implanted Layers

Using an Inline Four-Point Probe with the Single

Configuration

SEMI MF398 — Test Method for Majority Carrier

Concentration in Semiconductors by Measurement of

Wavelength of the Plasma Resonance Minimum

SEMI MF523 — Practice for Unaided Visual

Inspection of Polished Silicon Slices

SEMI MF525 — Test Method for Measuring

Resistivity of Silicon Wafers Using a Spreading

Resistance Probe

SEMI MF672 — Test Method for Measuring

Resistivity Profiles Perpendicular to the Surface of a

Silicon Wafer Using a Spreading Resistance Probe

SEMI MF723 — Practice for Conversion between

Resistivity and Dopant Density for Boron-Doped and

Phosphorus-Doped Silicon

SEMI MF1241 — Terminology of Silicon Technology

SEMI MF1392 — Test Method for Determining Net

Carrier Density Profiles in Silicon Wafer by

Capacitance-Voltage Measurements with a Mercury

Probe

SEMI MF1393 — Test Method for Determining Net

Carrier Density in Silicon Wafers by Miller Feedback

Profiler Measurements with a Mercury Probe

SEMI MF1726 — Guide for Analysis of

Crystallographic Perfection of Silicon Wafers