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SEMI MF1726-1103 © SEMI 2003 2 wafers may also be microscopically inspe cted before etching to count a nd classify visible imperfect ions. Wafers are then etched in a prefere ntial defect etchant solution. The etched sur…

SEMI MF1726-1103 © SEMI 2003 1

SEMI MF1726-1103

PRACTICE FOR ANALYSIS OF CRYSTALLOGRAPHIC PERFECTION

OF SILICON WAFERS

This standard was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the North American Silicon Wafer Committee. Current edition approved for publication by

the North American Regional Standards Committee on September 3, 2003. Initially available at

www.semi.org October 2003; to be published November 2003. Originally published by ASTM International

as ASTM F 1726-97. Last previous edition ASTM F 1726-02.

1 Purpose

1.1 The use of silicon crystals in many semiconductor

devices requires a consistent atomic lattice structure.

Crystal defects disturb local lattice energy conditions

that are the basis for semiconductor behavior. These

defects have distinct effects on essential semiconductor-

device manufacturing processes such as alloying and

diffusion.

1.2 Epitaxial growth processes are used extensively in

the manufacture of silicon electronic devices. Stacking

faults introduced during epitaxial growth can cause

“soft” electrical characteristics and preferential micro

plasma breakdowns in diodes.

1.3 Epitaxial defects are more clearly delineated with

the use of this destructive etching procedure. Epitaxial

wafers may however be classified nondestructively by

this method without the destructive preferential etching

and inspection steps.

1.4 This practice provides guidance regarding proce-

dures for analysis of crystal defects of silicon ingots

from which silicon wafers are cut.

1.5 This practice, together with the referenced

standards, may be used for process control, research

and development, and material acceptance purposes.

2 Scope

2.1 This practice covers the determination of the

density of crystallographic defects in unpatterned

polished and epitaxial silicon wafers. Epitaxial silicon

wafers may exhibit dislocations, hillocks, shallow pits

or epitaxial stacking faults, while polished wafers may

exhibit several forms of crystallographic defects or

surface damage. Use of this practice is based upon the

application of several referenced standards in a

prescribed sequence to reveal and count microscopic

defects or structures.

2.2 This practice is suitable for use with epitaxial or

polished wafers grown in either [111] or [100] direction

and doped either p or n-type with resistivity greater

than 0.005 Ω·cm.

2.3 This practice is suitable for use with epitaxial

wafers with layer thickness greater than 0.5 µm.

2.4 Additional requirements on the material to be

tested are listed in SEMI MF1810.

NOTICE: This standard does not purport to address the

safety issues, if any, associated with its use. It is the

responsibility of the user of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI MF95 — Test Method for Thickness of Lightly

Doped Silicon Epitaxial Layers on Heavily Doped

Silicon Substrates Using an Infrared Dispersive

Spectrophotometer

SEMI MF523 — Practice for Unaided Visual

Inspection of Polished Silicon Wafers Surfaces

SEMI MF1241 — Terminology of Silicon Technology

SEMI MF1809 — Guide for Selection and Use of

Etching Solutions to Delineate Structural Defects in

Silicon

SEMI MF1810 — Test Method for Counting

Preferentially Etched or Decorated Surface Defects in

Silicon Wafers

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Terminology

4.1 Defect-related terminology may be found in

SEMI MF1241.

5 Summary of Practice

5.1 Clean, unprocessed polished or epitaxial wafers are

selected. The wafers are examined under bright light

illumination to ensure that they are free from

contamination and obvious surface damage. Epitaxial

1 Currently available in Annual Book of ASTM Standards, Vol 10.05.

These documents have been transferred to SEMI, and will appear in

SEMI Standards Publications beginning with the November 2003

edition.

SEMI MF1726-1103 © SEMI 2003 2

wafers may also be microscopically inspected before

etching to count and classify visible imperfections.

Wafers are then etched in a preferential defect etchant

solution. The etched surface is again examined under

bright light illumination to identify patterns that may be

related to contamination or improper handling. The

imperfections highlighted by the preferential etchant are

then microscopically counted and classified.

6 Apparatus

6.1 Safety Equipment and Facility — for defect etching

as described in SEMI MF1809.

6.2 Wafer Inspection Facilities and Handling

Equipment — consistent with industry practice and

suitable for use with SEMI MF523.

7 Reagents and Materials

7.1 Refer to SEMI MF1809 for specific information on

reagents and materials.

8 Procedure

8.1 Select an unprocessed, polished or epitaxial wafer,

ready for use in the fabrication of electronic devices.

8.1.1 Open the wafer container in a particle-controlled

environment.

8.1.2 Transfer the wafer with a robotic tool or a

nonmetallic vacuum pencil, contacting the wafer edge

or back surface. Ensure that the front surface of the

adjacent wafer is not contacted during the removal.

NOTE 1: Any contact with the front surface of the adjacent

wafer can transfer contamination and generally scratch the

surface.

8.2 Preliminary Sample Inspection:

8.2.1 Inspect the first sample using high intensity light

conditions as described in SEMI MF523 to identify any

surface imperfections, scratches, or contamination

hazes that may interfere with the etching process or

confound the result. If any of these interferences are

detected, select a separate sample for analysis.

NOTE 2: These interferences can generate artifacts that may

be confused with the true defects.

8.2.2 Epitaxial Wafer, Nondestructive Defect Counting

— Inspect epitaxial wafers microscopically in

accordance with SEMI MF1810 before defect etching

to count most of the epitaxial stacking fault defects.

{100} {111}

NOTE: The orientation of the wafer defines the location and

direction of the line defects.

Figure 1

Slip Defects as Seen with Macroscopic High-

Intensity Light Inspection

NOTE 3: Epitaxial defects are more clearly delineated with

etching, but that is a destructive process.

8.3 Defect Etching

8.3.1 Epitaxial Wafers — Etch samples with epitaxial

layers greater than 2-µm thickness (as measured by

SEMI MF95) with removal of at least 0.5 µm to

highlight the crystal defects for quantification. Etch

samples with epitaxial layers less than 2 µm with

removal of no more than 50% of the layer thickness.

Other removal amounts are acceptable based upon

producer-consumer agreement. (See Note 4.)

8.3.2 Polished Wafers — The sample must be etched

with a removal of 5 to 15 µm to highlight the crystal

defects for quantification. Other removal amounts are

acceptable based upon producer/consumer agreement.

8.3.3 Refer to SEMI MF1809 for more etching

information.

NOTE 4: Crystal defects become more clearly visible for

unaided eye inspection with increased removal, but resolution

of the epitaxial induced defects is reduced with increasing

etch times.

8.4 Sample Inspection — Evaluate the preferentially

etched sample in two stages, macroscopic and

microscopic.

8.4.1 First inspect the sample macroscopically under

high intensity light conditions as described in

SEMI MF523 to detect patterns of defects, such as the

slip patterns shown schematically in Figure 1.

a b

NOTE: The orientation of the wafer does not define the

locations and direction of the line defects.

Figure 2

Typical Scratches (a) or Mechanically Induced

Defects (b) as Seen With High-Intensity Light

Inspection

8.4.2 Obtain a second sample if evidence of

mechanically or operator induced damage or

contamination is observed, because these artifacts

interfere with the identification of crystal growth

defects.

NOTE 5: Slip defects may be differentiated from the crystal

growth defects by insuring that all of the defects are aligned

as shown in Figure 1. Figure 2 shows the characteristics of

scratches or mechanical damage when viewed under high

intensity light conditions.

8.4.3 Microscopic Defect Counting — Count and report

the density of observed defects using SEMI MF1810.

9 Keywords

9.1 dislocation; epitaxy; grain boundaries; hillock;

polycrystalline imperfections; preferential etch; shallow

pit; silicon; slip; stacking fault

NOTICE: SEMI makes no warranties or

representations as to the suitability of the standards set

forth herein for any particular application. The

determination of the suitability of the standard is solely

the responsibility of the user. Users are cautioned to

refer to manufacturer' s instructions, product labels,

product data sheets, and other relevant literature,

respecting any materials or equipment mentioned

herein. These standards are subject to change without

notice.

By publication of this standard, Semiconductor

Equipment and Materials International (SEMI) takes no

position respecting the validity of any patent rights or

copyrights asserted in connection with any items

mentioned in this standard. Users of this standard are

expressly advised that determination of any such patent

rights or copyrights and the risk of infringement of such

rights are entirely their own responsibility.

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