semi合集-English.pdf - 第4428页

SEMI IN TERNA TIONA L STANDA RDS FLAT PANEL DISPLAY Sem iconduct or Equipm ent and Materials Inte rnational

SEMI F100-0705 © SEMI 2005 3

5.2.1 The valve and orifice tests must be applied with identical pressure sensors/flow meters.

5.2.2 Reproducibility and repeatability of measuring devices must rate 2 % or less of R.S.

5.2.3 Both the test valve and test orifice must have identical port connections.

5.3 Test Method/Procedure

5.3.1 In accordance to the test circuit of ¶5.2, flow rate is compared under the same pressure condition. Volume and

weight of accumulative flow can be compared without the use of a flow meter.

5.3.2 P1 is set 50kPa or more.

5.4 Qualification of Standard

5.4.1 The standard of diaphragm valves used with metric PFA tubes is determined by the flow rate Q1 of the tested

valve being greater than the flow rate Q2 of the standard orifice tested of ¶5.1. ( Q1 > Q2 / Q1 < Q2).

NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any

particular application. The determination of the suitability of the standard is solely the responsibility of the user.

Users are cautioned to refer to manufacturer's instructions, product labels, product data sheets, and other relevant

literature, respecting any materials or equipment mentioned herein. These standards are subject to change without

notice.

By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position

respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this

standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and

the risk of infringement of such rights are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction of

the contents in whole or in part is forbidden without express written

consent of SEMI.

SEMI INTERNATIONAL STANDARDS

FLAT PANEL DISPLAY

Semiconductor Equipment and Materials International

SEMI D3-91 © SEMI 1991, 2003 1

SEMI D3-91 (Reapproved 0703)

QUALITY AREA SPECIFICATION FOR FLAT PANEL DISPLAY

SUBSTRATES

This specification was technically reapproved by the Global Flat Panel Display Committee and is the direct

responsibility of the Japanese FPD Materials and Components Committee. Current edition approved by the

Japanese Regional Standards Committee on April 28, 2003. Initially available at www.semi.org June 2003;

to be published July 2003. Originally published in 1991.

1 Purpose

1.1 This document defines various areas on the pattern

surface of a flat panel display substrate and describes

their relationship. It assumes the existence of

terminology and a banking convention described in

other SEMI flat panel display documents.

2 Scope

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI D9 — Terminology for FPD Substrates

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Significance

4.1 The patterns placed on a flat panel display substrate

are expected to occur only in a specified, central area,

and certain requirements are applied in that area to both

the substrate and pattern quality. The substrate

peripheral area(s) outside this zone have different

specified properties. Defining the terms to apply and

the geometric relationship in these various areas will

assist the suppliers and users of substrates and

processing/inspection equipment.

5 Summary

5.1 A substrate edge length is defined in two

dimensions, L

and L

, with nominal and tolerance

values for each.

5.2 A quality area is defined by two dimensions, QA

and QA

, with nominal and tolerance values for each.

5.3 A fixed edge exclusion area is defined for the

substrate edges to be placed against reference (also

called “banking”) pins.

5.4 Two variable edge exclusion areas result from

combining the above three dimension sets.

6 Procedure

6.1 Locate the properties in Sections 6.2–6.4 relative to

the substrate origin, using the nominal values assigned

by the substrate specification.

6.2 Let L

= the substrate edge length in the x-

direction, and

= the substrate edge length in the y-direction. (See

Figure 1.)

6.3 Let EF

= the fixed edge exclusion area along the

substrate’s lower edge, and

= the fixed edge exclusion area along the

substrate’s left edge.

6.4 Let QA

= the quality area’s edge length in the x

direction, and

= the quality area’s edge length in the y direction.

6.5 Then EV

and EV

, the variable edge exclusions,

are not specified. They result from the interaction of

substrate tolerance variations from nominal with the

fixed location origin.