semi合集-English.pdf - 第5258页

SEMI M41-1101 © SE MI2000, 2001 15 Table 7 Example: Soi W afer Surface V isual Inspe ction Criteria Criterion Items Allowed Quantity ( Pe r 150 mm Wafer ) Description Haze NONE Slip < 4 2 mm width an d < 15 mm leng…

100%1 / 7923
SEMI M41-1101 © SEMI 2000, 2001 14
MHz frequency, 5 nm void gap and 50 µm void diameter can
be detected.
NOTE 16: Void is defined as “empty space” that is due to the
imperfect bonding at Si/SiO
2
and SiO
2
/ SiO
2
interface. This
void should be discriminated from the splitting at bonding
strength test.
NOTE 17: Void can be only evaluated during SOI wafer
processing, not at the shipping.
8.9 Bonding Strength
8.9.1 Tensile Testing Method — Bonding strength is
defined and evaluated by tensile strength (kgf/cm
2
)
which is needed to split the bonding interface vertically.
Details of the test structure and the test method should
be determined by negotiation between wafer users and
wafer suppliers.
Table 6 Test Summary Table
Parameter Reference Method
Wafer Diameter F613-93 Optical Comparator
Wafer Thickness F533-96, F1530-94 Thick. Gage, Auto. Noncontact Scan.
Total Thickness Variation
LTV
F1530-94 Automated Noncontact Scanning
Warp F1390-92 Automated Noncontact Scanning
Crystal Orientation
Top Silicon Film (SOI)
Base Wafer
F26-87a (1993) X-ray Diffraction
Substrate Type / Dopant F42-93 Hot-Probe (Test Method A)
Substrate Resistivity F43-93, F84-93, F1527-94 4 Point Probe
Substrate RRG F81-95 4 Point Probe
Top Si Film Thickness Section 8.1 Reflective Spectroscopy or FTIR
Crystal Defect (OSF) Section 8.2, (JIS H 0609 :1994 B) Cr-free Etch / Optical Microscopy
Buried Ox defects Section 8.3, (SEMI M34) (a) Cu Decoration, (b) BOX Capacitor
Metal Contamination
(per unit area)
Section 8.4, (F1526-95) TXRF, AAS/ICP-MS
Particle Density ( LPD ) Section 8.5 (F1620-96) Light Scattering Tomography
( Automated Particle Counter )
Haze F523-93 (see NOTE 1), F154-94 Visual Inspection
Slip F523-93 (see NOTE 1), F154-94 Visual Inspection
Scratches F523-93 (see NOTE 1), F154-94 Visual Inspection
Chips / Cracks F523-93 (see NOTE 1), F154-94 Visual Inspection
Pits and Dimples F523-93 (see NOTE 1), F154-94 Visual Inspection
Mounds F523-93 (see NOTE 1), F154-94 Visual Inspection
Orange peel F523-93 (see NOTE 1), F154-94 Visual Inspection
Particle Density ( LPD ) F523-93 (see NOTE 1), F154-94 Visual Inspection
Contamination ( Both Side ) F523-93 (see NOTE 1), F154-94 Visual Inspection
Surface Roughness Section 8.6 AFM
Inclusions Section 8.7 SIMS
Voids Section 8.8 Scanning Acoustic Tomography
Bonding Strength Section 8.9 Tensile Strength
NOTE 1: Users and suppliers may agree on the non-SOI edge area for these specifications. For example the area within 6 mm proximity of the
wafer edge may be excluded.
SEMI M41-1101 © SEMI2000, 200115
Table 7 Example: Soi Wafer Surface Visual Inspection Criteria
Criterion Items Allowed Quantity ( Per 150 mm Wafer ) Description
Haze NONE
Slip < 4
2 mm width and < 15 mm length
Scratches NONE
Chips / Cracks < 3 for @ 0.5 mm circumferential x 0.3 mm length Edge : Base Wafer
Pits and Dimples NONE
Particle Density ( LPD ) < 30 for @ > 0.2 µm <0.17 / cm
2
for 150 mm Wafer
Contamination NONE Both Surface and Backside
NOTE 1: The surface visual inspection is conducted under the collimated bright light.
NOTE 2: Non-SOI edge area (E.E. ) of 6 mm is applied to the criterion items except for edge chips/cracks.
NOTE 3: The whole wafer (Top silicon film and Base wafer) is inspected except for edge chips/cracks.
Table 8 Soi Electrical Parameters
Parameters Reference Value Method
Photo-conductivity Lifetime Section 9.1 To be determined µ-PCD
BOX Breakdown Section 9.2 To be determined I-V
BOX Charge Section 9.3 To be determined C-V
BOX Surface States Section 9.4 To be determined C-V
Doping Density
Top silicon film, Base wafer
Section 9.5 To be determined SIMS or 4 pt. probe
9 Electrical Parameters
9.1 Photo-conductivity Lifetime
9.1.1 Test Method:
µ-PCD method
9.1.1.1 Excess carriers that are created in the wafer by a light pulse increases the conductivity of the sample. When
the light is turned off, the conductivity is decreased by the carrier recombination. This phenom-enon is monitored
by means of microwave reflectance. The microwave detects an exponential decay in conduc-tivity, from which a
decay constant is determined.
9.1.2 The effective recombination lifetime τ
eff
is given by the following expression:
1/τ
eff
= 1/τ
B
+ 1/(τ
S
+ τ
D
)
τ
S
= d/(S
Si/Box
+ S
Si
), τ
D
= d/π
2
D
Where τ
B
is bulk recombination lifetime, τ
S
is surface recombination lifetime, τ
D
is diffusion lifetime, S
Si/Box
is
recombination velocity at the Box interface, S
Si
is recombination velocity at the silicon surface, D is diffusion
coefficient and d is top silicon film thickness.
9.1.3 The wavelength of the light has to be selected, depending on the top silicon film thickness (see Table 9).
9.2 Box Breakdown Voltage
9.2.1 Test Structure –– Box capacitor having an area (Ex. 1 cm
2
).
9.2.2 Test Method: Staircase I-V Measurement –– Voltage is stepwise increased in one-volt increments from zero to
the (+/-) specified voltage. Details of the test structure and the test method are determined by negotiation between
wafer users and wafer suppliers.
9.3 Box Charge
9.3.1 Test Structure — Box capacitor having an area (Ex. 1 cm
2
).
SEMI M41-1101 © SEMI 2000, 2001 16
9.3.2 Test method — MOS high-frequency C-V measurement of a Box capacitor normally yields a flat band
voltage. Details of the test structure and the test method are determined by negotiation between wafer users and
wafer suppliers.
9.4 Buried Oxide Fast Interfaces State Density
9.4.1 Test Structure — Box capacitor having an area. (Ex. 1 cm
2
)
9.4.2 Test Method — High-Low Frequency MOS C-V.
9.4.3 If care is taken in their fabrication to minimize oxide surface damage and contamination during silicon
etching, good quality quasi-static MOS C-V curves can be measured. From comparison of high and low frequency
C-V curves, midgap interface state density can be determined. Details of the test structure and the test method are
determined by negotiation between wafer users and wafer suppliers.
9.5 Doping Density
9.5.1 Test Method — SIMS
9.5.1.1 Be careful of electrical charging up of test pieces due to the existence of BOX, the difference of detecting
sensitivity between silicon and silicon dioxide, and the existence of disturbance ions such as Si
30
H
1
in case of P
31
measurement.
Table 9 Relationship Between Wavelength of the Light and Penetration Depth
Wavelength [nm] 450 532 635 670 780 820 850
Depth [µm] ~ 0.8 ~ 1.4 ~ 3.0 ~ 4.0 ~ 10.0 ~ 14.0 ~ 18.0
9.5.2 Test Method — Four point probe
9.5.2.1 By contacting the equally spaced four point probes with a wafer and by supplying current between the outer
two probes, the voltage difference between the inner two probes is measured. The silicon resistivity ρ is determined
by the following equation (JIS H0602):
ρ= πV/ln2•I•d[Ωcm] if probe interval >> top silicon film thickness: d
9.5.3 The specific test method should be determined between wafer users and wafer suppliers.
10 Packing and Marking
10.1 Special packing requirements shall be subject to agreement between the users and the suppliers. Otherwise all
wafers shall be handled, inspected, and packed in such a manner as to avoid chipping, scratches and contamination,
and in accordance with the best industry practices to provide sample protection against damage during shipment.
10.2 The wafer supplied under these specifications shall be identified by appropriately labeling on the outside of
each box or other container and each subdivision thereof in which it may be reasonably expected that the wafers will
be stored prior to further processing. Identification marks, codes, symbols and content shall be agreed upon between
users and suppliers.
NOTICE: SEMI makes no warranties or representations as to the suitability of the standard set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant
literature respecting any materials mentioned herein. These standards are subject to change without notice.
The user’s attention is called to the possibility that compliance with this standard may require use of copyrighted
material or of an invention covered by patent rights. By publication of this standard, SEMI takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.