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SEMI M50-1104 © SEMI 2001, 2004 8 A1-10.5 Calculate and record the scanner XY uncertainty as follows: ) ( 2 2 y x S S S   (A4) NOTICE: SEMI makes no warranties or represen tations as to the suitability o f the standard…

SEMI M50-1104 © SEMI 2001, 2004 7

A1-7 Apparatus

A1-7.1 SSIS under test — as defined in Section 7 of this standard with characteristics as outlined in SEMI M53.

A1-8 Reference Wafer

A1-8.1 The reference wafer shall meet the dimensional requirements of SEMI M1 for the largest diameter of wafer

to be inspected by the SSIS under test.

A1-8.2 The surface of the reference wafer shall contain at least ten LLSs (particles or pits) of a size (LSE) well

above the threshold, so that the capture rate is ~100%.

A1-8.3 These ten or more LLSs must be distributed over the entire surface of the wafer.

A1-9 Procedure

A1-9.1 Load the reference wafer into the SSIS with the fiducial (flat or notch) located in accordance with

customary operating procedures of the laboratory conducting the test.

A1-9.2 Scan the wafer and create a data set containing the reported x and y coordinates of each of the ten or more

selected LLSs.

A1-9.3 Call this scan, Scan 1.

A1-9.4 Repeat the scans, nine more times, and create nine more data sets containing the reported x and y

coordinates of each of the ten or more selected LLSs.

A1-10 Calculations

A1-10.1 Examine each of the data sets (either as wafer maps or mathematically) to determine that coordinate pairs

for each of the ten or more LLSs being analyzed appear in each of the ten scans.

A1-10.2 Delete from the data any coordinate pair that does not appear in all ten data sets.

A1-10.3 Determine the average and the sample standard deviation of x and y coordinates of each of the N remaining

coordinate pairs as follows:





iki

xx and





iki

yy (A1)







)(

iikxi

xxs

and







)(

iikyi

yys

(A2)

where:

= average of the ten x coordinates reported for the i

LLS,

= average of the ten y coordinates reported for the i

LLS,

= sample standard deviation of the ten x coordinates reported for the i

LLS,

= sample standard deviation of the ten y coordinates reported for the i

LLS, and

k = scan number (from 1 to 10).

A1-10.4 Calculate the pooled sample standard deviations of the reported x and y coordinates as follows:



















xix

and



















yiy

(A3)

where:

= pooled sample standard deviation of the ten x coordinates reported for the N LLSs,

= pooled sample standard deviation of the ten y coordinates reported for the N LLSs, and

N = number of coordinate pairs appearing in all ten scans.

SEMI M50-1104 © SEMI 2001, 2004 8

A1-10.5 Calculate and record the scanner XY uncertainty as follows:

)(

SSS  (A4)

NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any

particular application. The determination of the suitability of the standard is solely the responsibility of the user.

Users are cautioned to refer to manufacturer's instructions, product labels, product data sheets, and other relevant

literature, respecting any materials or equipment mentioned herein. These standards are subject to change without

notice.

By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position

respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this

standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and

the risk of infringement of such rights are entirely their own responsibility.

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consent of SEMI.

SEMI M51-0303 © SEMI 2002, 2003 1

SEMI M51-0303

TEST METHOD FOR CHARACTERIZING SILICON WAFERS BY GATE

OXIDE INTEGRITY

This test method was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional

Standards Committee on January 10, 2003. Initially available at www.semi.org January 2003; to be

published March 2003. Originally published July 2002.

NOTICE: This document was rewritten in its entirety

in 2002.

1 Purpose

1.1 This test method describes procedures for

characterizing silicon wafers to determine Gate Oxide

Integrity (GOI). This test method is effective in

evaluating the density of Crystal Originated Particles

(COP) in polished Czochralski (CZ) silicon wafers that

influence GOI.

2 Scope

2.1 This test method provides detailed procedures for

characterizing silicon wafers using GOI. This test

method describes standard procedures for Metal Oxide

Semiconductor (MOS) fabrication, electrical

measurement, analysis, and reporting.

2.2 Thermally grown gate oxide films with gate oxide

thicknesses ranging from 20–25 nm and polysilicon

electrodes are used as MOS capacitors. Discussion of

the gate oxide thickness is given in a later section.

2.3 Time Zero Dielectric Breakdown (TZDB) is used

as the electrical characterization method of MOS

capacitors.

2.4 It is well known that oxygen precipitates are also a

source of gate oxide defects.

However, this is beyond

the scope of this standard because the as-received

wafers contain only a small amount of oxygen

precipitate.

NOTE 1: The polysilicon film can make standard test results

applicable to the testing of wafers used to fabricate integrated

circuits rather than other metal electrodes because polysilicon

electrodes are commonly used in actual devices.

NOTE 2: The TZDB method measures oxide breakdown

electric fields using MOS capacitors. The density of COPs

can be estimated from a histogram of the breakdown electric

field.

NOTE 3: For a detailed discussion of sample structures for

this test method, the reader is referred to EIA/JEDEC

Standard 35-1. In general, the three most likely sample

1 K.Yamabe and K.Taniguchi, “Time-Dependent Dielectric

Breakdown of Thin Thermally Grown SiO2 Films”, J. Solid St.

Circuits, SC-20, 343 (1983).

structures are simple planar MOS capacitors, MOS capacitors

with various isolation structures (for example, local oxidation

of silicon (LOCOS), shallow trench isolation (STI)), and field

effect transistors (FET). For the purpose of silicon wafer

characterization, the simple planar MOS capacitor structure is

preferable. This is because with the various isolation

structures and FET, silicon wafers sometimes receive thermal

treatments during the complicated sample fabrication process.

Therefore, it is questionable to look upon a measurement of

one of the latter two wafers as the starting silicon wafer

characterization.

NOTE 4: This standard is based on round robin results

among silicon wafer manufacturers. In general, the COPs in

the polished CZ silicon substrates strongly influence the

TZDB histogram of the gate oxide. This GOI test method

strongly depends on wafer-surface/near-surface crystal

defects, contaminations, particles and cleanliness of the MOS

fabrication processes environment. Cleanliness of the

processes environment should be evaluated because it

strongly affects the MOS characteristics. (See Section 5.2.1

and Related Information 1).

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI C3.6 ― Standard for Phosphine in Cylinders

99.98% Quality (Provisional)

SEMI C3.21 ― Standard for Carbon Tetrafluoride in

Cylinders (Provisional)

SEMI C3.22 ― Standard for Oxygen, 99.5% Quality

SEMI C3.23 ― Standard for Oxygen, 99.98% Quality

SEMI C3.28 ― Standard for Nitrogen, VLSI Grade in

Cylinders, 99.9996% Quality

SEMI C3.41 ― Standard for Oxygen, Bulk, 99.9998%

Quality (Provisional)

SEMI C3.49 ― Standard for Bulk Nitrogen,

99.99999% Quality (Provisional)

SEMI C3.54 ― Gas Purity Guideline for Silane