semi合集-English.pdf - 第5396页

SEMI M56-1103 © SEMI 2003 11 The cost difference in operating Ga uge A rather than Gauge B in this exampl e is, on average, $1.45 pe r wafer. Table R4-1 Empirical Distribution of SFQR Measurement s and Calculations of α …

100%1 / 7923
SEMI M56-1103 © SEMI 2003 10
RELATED INFORMATION 4
EXAMPLE OF CALCULATION ACCORDING TO PROCEDURE
NOTICE: This related information is not an official part of SEMI M56. It was derived from task force
deliberations during the development of the document. This related information was approved for publication by
full letter ballot procedures on September 3, 2003.
R4-1 This example relates to the calculation of the cost
components due to misclassification caused by
measurement variability in flatness measurement during
wafer manufacturing. The following premises are
made:
R4-1.1 A wafer manufacturer must supply a customer
with a specific number of wafers that conform to a site
flatness specification of 0.13 µm
, SFQR as defined in
SEMI M1.
R4-1.2 Most wafers produced do conform to the
specification. Due to variability in the manufacturing
process, some wafers do not conform to the
specification.
R4-1.3 The flatness measurement step is near the end
of the wafer manufacturing process. It follows surface
polishing and precedes final cleaning, surface
inspection, and packaging.
R4-1.4 All of the wafers are measured for site flatness.
The measurement data is used to determine if wafers
are passed for further processing and shipment or if
they are failed and scrapped without further processing.
This example premises no rework for failed wafers.
R4-1.5 The customer is always able to detect a non-
conforming wafer. When a non-conforming wafer is
detected, it is returned to the manufacturer and a
replacement wafer must be supplied to satisfy the
specified order quantity.
R4-2 The following steps follow the procedures
outlined in Section 6.
R4-2.1
Estimation of Process Distribution — A total of
17,698 observations was made on flatness
measurements. An empirical estimate of the flatness
CDF was calculated from these data and is shown in the
column of Table R4-1 labeled F(x).
R4.2.2 Estimation of Bias and Variance for Each
Gauge Compared — Two gauges are available. Gauge
A has zero bias and a measurement variability of
σ
A
= 0.00433, which results in a P/T ratio of 10%,
calculated in accordance with SEMI M27 for a single
sided distribution. Gauge B also has zero bias, but has
a measurement variability of
σ
B
= 0.00867 or a P/T
ratio of 20%. Let the distribution of the measurement
variability for the two gauges be normally distributed
with a mean of zero and standard deviations given
above.
R4-2.3 Calculation of
α
and
β
— To calculate
α
and
β
,
one needs to estimate
f(x) and Φ(z), where
z = (USL
−
x)/
σ
M
.
The values in the column labeled f(x) are derived by
dividing the value in the count column by the total
number of observations. σ(z) is calculated from the
normal CDF using the numbers in the first column as x,
0.13 as the USL, and either σ
A
= 0.00433 or
σ
B
= 0.00867 for σ
M
, depending on whether Gauge A or
Gauge B is used. To calculate
α
, for each row multiply
f(x) by 1
−
Ф(z) and sum over all rows at or below the
specification limit. To calculate β, for each row
multiply f(x) by Ф(z) and sum over all rows above the
USL. The calculations for
α
and
β
for the two P/T
ratios of 10% and 20% can also be found in Table R4-1.
R4-2.4 Decision Model — One of four situations may
occur depending on the true flatness of the wafer,
conforming or nonconforming, and the decision made
based on the output from the metrology equipment,
pass or fail. Two correspond to correct actions: passing
a conforming item and failing a nonconforming item.
Zero incremental cost is associated with correct
classification. The two situations associated with
misclassification, passing a nonconforming item and
failing a conforming item, have actual incremental
costs.
R4-2.5
Estimation of Costs — For purposes of
illustration, let the cost of failing a conforming wafer
(c
fc
) be $300 and the cost of passing a nonconforming
(c
pn
) wafer be $220. The cost of ownership due to mea-
surement variability and bias can then be calculated as:
cost = c
fc
P(fail,conforming)+c
pn
P(pass, nonconforming)
= c
fc
α
+ c
pn
β
R4-2.6 Calculation of Costs — The cost components
due to measurement variability for Gauge A and Gauge
B are:
cost
A
= c
fc
α
A
+ c
pn
β
A
=
(300)(0.01042530) + (220)(0.00011698) = 3.1533
cost
B
= c
fc
α
B
+ c
pn
β
B
=
(300)(0.01428055) + (220)(0.00145950) = 4.6053
SEMI M56-1103 © SEMI 2003 11
The cost difference in operating Gauge A rather than Gauge B in this example is, on average, $1.45 per wafer.
Table R4-1 Empirical Distribution of SFQR Measurements and Calculations of
α
and
β
for Flatness
Measuring Gauges with P/T = 10% and P/T = 20%
SFQR f (x ) F (x )
(
µ
m) (PDF) (CDF) z
Φ
(z ) f (x )(1-
Φ
(z )) f (x )
Φ
(z ) z
Φ
(z ) f (x )(1-
Φ
(z )) f (x )
Φ
(z )
0.01 0 0.0000 0.0000 27.6923 1.0000E+00 0.0000E+00 0.0000E+00 13.8462 1.0000E+00 0.0000E+00 0.0000E+00
0.02 89 0.0050 0.0050 25.3846 1.0000E+00 0.0000E+00 5.0288E-03 12.6923 1.0000E+00 0.0000E+00 5.0288E-03
0.03 772 0.0436 0.0486 23.0769 1.0000E+00 0.0000E+00 4.3621E-02 11.5385 1.0000E+00 0.0000E+00 4.3621E-02
0.04 1,703 0.0962 0.1449 20.7692 1.0000E+00 0.0000E+00 9.6226E-02 10.3846 1.0000E+00 0.0000E+00 9.6226E-02
0.05 2,389 0.1350 0.2799 18.4615 1.0000E+00 0.0000E+00 1.3499E-01 9.2308 1.0000E+00 0.0000E+00 1.3499E-01
0.06 2,752 0.1555 0.4354 16.1538 1.0000E+00 0.0000E+00 1.5550E-01 8.0769 1.0000E+00 5.1791E-17 1.5550E-01
0.07 2,556 0.1444 0.5798 13.8462 1.0000E+00 0.0000E+00 1.4442E-01 6.9231 1.0000E+00 3.2112E-13 1.4442E-01
0.08 2,298 0.1298 0.7096 11.5385 1.0000E+00 0.0000E+00 1.2985E-01 5.7692 1.0000E+00 5.1858E-10 1.2985E-01
0.09 1,687 0.0953 0.8049 9.2308 1.0000E+00 0.0000E+00 9.5322E-02 4.6154 1.0000E+00 1.8720E-07 9.5321E-02
0.10 1,189 0.0672 0.8721 6.9231 1.0000E+00 1.4938E-13 6.7183E-02 3.4615 9.9973E-01 1.8045E-05 6.7165E-02
0.11 789 0.0446 0.9167 4.6154 1.0000E+00 8.7554E-08 4.4581E-02 2.3077 9.8949E-01 4.6846E-04 4.4113E-02
0.12 524 0.0296 0.9463 2.3077 9.8949E-01 3.1112E-04 2.9297E-02 1.1538 8.7572E-01 3.6797E-03 2.5928E-02
0.13
358 0.0202 0.9665 0.0000 5.0000E-01 1.0114E-02 1.0114E-02 0.0000 5.0000E-01 1.0114E-02 1.0114E-02
0.14 197 0.0111 0.9777 -2.3077 1.0508E-02 1.1014E-02 1.1697E-04 -1.1538 1.2428E-01 9.7478E-03 1.3834E-03
0.15 126 0.0071 0.9848 -4.6154 1.9639E-06 7.1194E-03 1.3982E-08 -2.3077 1.0508E-02 7.0446E-03 7.4812E-05
0.16 87 0.0049 0.9897 -6.9231 2.2234E-12 4.9158E-03 1.0930E-14 -3.4615 2.6860E-04 4.9145E-03 1.3204E-06
0.17 67 0.0038 0.9935 -9.2308 0.0000E+00 3.7857E-03 0.0000E+00 -4.6154 1.9639E-06 3.7857E-03 7.4348E-09
0.18 52 0.0029 0.9964 -11.5385 0.0000E+00 2.9382E-03 0.0000E+00 -5.7692 3.9938E-09 2.9382E-03 1.1735E-11
0.19 38 0.0021 0.9986 -13.8462 0.0000E+00 2.1471E-03 0.0000E+00 -6.9231 2.2234E-12 2.1471E-03 4.7740E-15
0.20 25 0.0014 1.0000 -16.1538 0.0000E+00 1.4126E-03 0.0000E+00 -8.0769 3.3307E-16 1.4126E-03 4.7049E-19
Sum = 17,698 1.0000
USL = 0.13
µ
m
For P/T = 10%,
σ
Μ
=
σ
A
= 0.10 x 0.13/3 = 0.00433
F
or P/T = 20%,
σ
Μ
=
σ
B
= 0.20 x 0.13/3 = 0.00867
P/T = 3
σ
Μ
/USL
α
A
= 1.0425E-02
α
B
= 1.4281E-02
β
A
= 1.1698E-04
β
B
= 1.4595E-03
P/T = 10% P/T = 20%
Count
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer's instructions, product labels, product data sheets, and other relevant
literature, respecting any materials or equipment mentioned herein. These standards are subject to change without
notice.
By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M57-0705 © SEMI 2004, 2005 1
SEMI M57-0705
GUIDE FOR SPECIFYING SILICON ANNEALED WAFERS
This guide was technically approved by the global Silicon Wafer Committee. This edition was approved for
publication by the global Audits and Reviews Subcommittee on April 7, 2005. It was available at
www.semi.org in June 2005 and on CD-ROM in July 2005. Originally published July 2004; previously
published March 2005.
1 Purpose
1.1 A number of device manufacturers utilize silicon annealed wafers to gain improved device characteristics. This
guide provides information for developing specifications for silicon annealed wafers used to fabricate semiconductor
devices and integrated circuits.
2 Scope
2.1 This guide covers dimensional, electrical, chemical, and structural properties of silicon annealed wafers for
180 nm, 130 nm, and 90 nm device technology generations.
2.2 Based on the guidance herein, the user of the guide can generate specifications for silicon annealed wafers.
2.3 One of the reasons for using annealed wafers is to allow a reduction in the crystal originated particles (COP)
near the top surface region of the wafer. Currently, only the COP surface density can be estimated.
2.4 The width of the denuded zone (DZ) free of bulk micro defects (BMD) is also an important parameter.
However, there is no standardized method to evaluate this characteristic at the present time.
2.5 The complete EDI Code List for items in the Order Form appropriate to silicon wafers, including annealed
wafers, can be found in SEMI M18.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the
responsibility of the user of this standard to establish appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
3 Referenced Standards and Documents
3.1 SEMI Standards
SEMI M1 — Specifications for Polished Monocrystalline Silicon Wafers
SEMI M18 — Format for Silicon Wafer Specification Form for Order Entry
SEMI M33 — Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means
of Total Reflection X-Ray Fluorescence Spectroscopy (TXRF)
SEMI M35 — Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated
Inspection
SEMI M45 — Provisional Specification for 300 mm Wafer Shipping System
SEMI M53 — Practice for Calibrating Scanning Surface Inspection Systems Using Depositions of Monodisperse
Polystyrene Latex Sphere on Unpatterned Semiconductor Wafer Surfaces
SEMI M58 — Test Method for Evaluating DMA-Based Particle Deposition Systems and Processes
SEMI M59 — Terminology for Silicon Technology
SEMI MF81 — Test Method for Measuring Radial Resistivity Variation on Silicon Wafers
SEMI MF391 — Test Methods for Minority-Carrier Diffusion Length in Extrinsic Semiconductors by Measurement
of Steady-State Surface Photovoltage
SEMI MF523 — Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces
SEMI MF951 — Test Method for Determination if Radial Interstitial Oxygen Variation in Silicon Wafers