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SEMI E78-1102 © SEMI 1998, 2002 14 to those establi shed by the ESD Association Stan dards ESD STM 5.1 (for HBM), ESD S5.2 (for MM), and MIL-STD-883, C/30 15.7-method 8. The ESD Association is presently considering tw o …
SEMI E78-1102 © SEMI 1998, 2002 13
RELATED INFORMATION 1
STATIC CHARGE PROBLEMS
NOTE: The material contained in this related information is not an official part of SEMI E78 and is not intended to modify or
supersede the guide in any way. These notes are provided as a source of information to aid in the application of the guide, and are
to be considered reference material. Determination of the suitability of the material is solely the responsibility of the user.
R1-1 ESD Damage
Contributed by Leo G. Henry, Ph.D., Advanced Micro
Devices, EOS/ESD/LU/EMC Department, Sunnyvale,
CA 94538, leogesd@pacbell.net.
R1-1.1 Introduction — ESD damage to devices occurs
when they come into contact with personnel and
equipment. Either may store a residual charge large
enough to destroy the device if a discharge occurs. In
the semiconductor industry, it has been established that
a significant proportion of customer field returns are
attributed to damage resulting from ESD.
R1-1.2 Description of ESD Damage Mechanisms —
ESD failures are the result of either a current-induced
phenomenon or a charge-induced phenomenon, and the
damage can either be junction, contact, dielectric or
oxide related. The apparent similarity in current-
induced damage resulting from ESD due to human
body model discharges (HBM) or machine model
discharges (MM) results from the thermal nature of
both of these process. The HBM and MM damages
result when the temperature (joule heating) of the
region dissipating the ESD pulse energy reaches a
critical value and melting occurs.
R1-1.2.1 Charge-induced phenomena are predicted by
the charged device model (CDM). For CDM type
discharges, oxide punch through occurs when the ESD
voltage applied across the oxide creates a high enough
field to break down the oxide. Excessive current flow
results, causing an oxide short, but there is no heat
transfer (adiabatic process).
R1-1.2.2 It should be noted here that the time duration
for typical ESD events from charged objects and
personnel ranges from 10 to 100 nanoseconds, while
CDM type events occur in less than 1 nanosecond.
R1-1.3 Device Testing Models
R1-1.3.1 Human Body Model (HBM) — The Human
Body Model is the oldest and the most widely used of
the three ESD models. The model attempts to replicate
the discharge from a real human when the latter touches
a device that is at a lower potential. The human
capacitance and resistance have been ideally chosen to
be 100 picofarads and 1500 ohms respectively. The
values were chosen after measurements were made on
humans in varying positions with respect to their
surroundings. The resulting discharge waveform has a
double exponential shape with risetime range of 2–10
nsec and a decay constant (1/e position) of 150 ± 20
nsecs. The typical peak currents range from 0.67 Amps
at 1000 volts to 2.67 Amps at 4000 volts.
R1-1.3.2 Machine Model (MM) — The Machine
Model is described by Electronic Industries Association
of Japan (EIAJ) as a worst case HBM. The model
attempts to replicate the discharge from a metallic arm
of an automatic handler coming into contact with the
metallic leads of a semiconductor device which is at a
lower potential. A capacitance of 200 picofarads and
ideally zero resistance produces a sinusoidal decaying
waveform with an effective pulse duration of 200 nsec.
The typical peak currents range from 1.75 Amps at 100
volts to 14.0 Amps at 800 volts. Note that MM failures
occur at 5–10 times lower voltage than HBM.
R1-1.3.3 Charged Device Model (CDM) — The
Charged Device Model in its purest form is actually a
field induced model because the device is actually part
of model. This model attempts to describe a device
which itself becomes charged due to an external field,
or due to triboelectric charging of the device surfaces.
During discharge, the parasitics (capacitance,
inductance and impedance) in the device play a
significant role in the resulting failure. The discharge
pulse is a sinusoidal waveform with an extremely fast
risetime of less than 500 picoseconds. The waveform
decays rapidly with a total pulse duration of less than 5
nano-seconds. The peak currents range from 2.0 Amps
at 250 volts charging voltage, to 18.0 Amps at 2000
volts charging voltage.
R1-1.3.4 Correlation Between Models — There is
much debate on whether or not there is any type of
correlation between HBM and MM. While some
companies report a correlation of roughly 10:1 between
the two models, other companies have seen anywhere
from 5–20:1 differences in passing voltages between
the two models. There is also no established voltage
correlation between CDM damage and HBM or MM
ESD events. In equipment, ESD damage events will be
related to the MM or CDM types of ESD. Users will
need to determine the type of ESD hazard to their
devices and choose the test method accordingly.
R1-1.4 ESD Laboratory Simulation Testing
R1-1.4.1 Description of Test Methods — Test
procedures discussed here for ESD simulation conform
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to those established by the ESD Association Standards
ESD STM 5.1 (for HBM), ESD S5.2 (for MM), and
MIL-STD-883, C/3015.7-method 8. The ESD
Association is presently considering two documents
related to CDM Testing. Details are to be found in these
standards.
R1-1.4.1.1 Devices are qualified at a level
corresponding to the highest ESD stress they are able to
withstand. These levels are discussed in more detail in
Appendix A1-2.1.
R1-1.4.2 Simulation Test Results — In general all units
must be data-logged both pre- and post-stress test. Any
leakage current equal to or greater than a specific
amount (company dependent — typically 10 micro-
amps or less) is “flagged” as a failure, and any current
shift greater than about 200 nano-Amp is marked on the
record.
R1-1.4.3 HBM Stress Testing — An R-C network is
used to simulate the ESD event. In an HBM ESD
Simulator, a high voltage is used to charge the capacitor
(100 pF) which discharges through the resistor (1500
ohms) into the device under test. The present draft
standard (1997) requires a minimum of two discharges
(1 positive and 1 negative) per voltage level.
R1-1.4.4 MM Stress Testing — An R-C network is also
used in the MM ESD Simulator for ESD testing. High
voltage charges the capacitor (200 pF) which
discharges through the short wire (zero ohm) into the
device under test. The present standard requires a
minimum of six discharges (3 positive and 3 negative).
R1-1.4.5 CDM Stress Testing — The package and
leadframe of the device are charged by direct charging
or field induction. For the Direct Charging Method,
direct contact is made to one of the device leads
connected to the substrate or bulk material of the
device. The device is then discharged via a one ohm
resistor to ground.
R1-1.4.5.1 For the Field Induced Method, the device is
placed on a metallic charging plate with the device
packaging material touching the plate. The potential of
the device is raised by applying a voltage to the
charging plate. The induced voltage on the device is
discharged to ground through a 1 ohm resistor that
contacts each device lead. The present draft standard
(1996) requires a minimum of 6 discharges (3 positive
and 3 negative) from each device lead.
R1-1.5 Examples of Damage from Device Testing
R1-1.5.1 HBM ESD Damage
Figure R1-1
Example of HBM Damage
R1-1.5.1.1 In this example of HBM damage (refer to
Figure R1-1), de-processing (removal of the processed
layers) down to the poly level and very high
magnification (SEM) examination were required in
order to see the failure site morphology of arcing from
source to drain within the ESD protective structures.
The electrical characteristics found were: resistive
shorts, leakages, low breakdown voltages and Icc
failures.
R1-1.5.2 MM ESD Damage
Figure R1-2
Example of MM Damage
R1-1.5.2.1 In the above MM example (refer to Figure
R1-2), the damage was more severe than for HBM. De-
processing down to the poly level and the SEM
examination showed the failure site morphology of
large deep pits occurring at the contact(s) suggesting
SEMI E78-1102 © SEMI 1998, 2002 15
high current parasitic bipolar action deep in the
substrate and also within the ESD protective structures.
The electrical characteristics found also resistive shorts,
leakages, low breakdown voltages and Icc failures.
R1-1.5.3 CDM ESD Damage
Figure R1-3
Example of CDM Damage
R1-1.5.3.1 In the above CDM example (refer to Figure
R1-3), the gate oxide damage is seen as a unique failure
signature beyond the input protection structures at an
internal location of the die. Most often the oxide failure
is located beneath the poly at the field oxide edge, or is
located at the poly edge adjacent to the source/drain
junction. To date all CDM ESD damage has been found
in the gate oxide at the input buffer circuitry.
R1-1.6 References
Cook, C., Daniel, S., Proceedings EOS/ESD
Symposium, Dallas, TX (1992), p. 149–157
Euzent, B.L., Maloney, T.J., Donner II, J.C.,
Proceedings EOS/ESD Symposium, Las Vegas, NV
(1991), p. 59–64
Morgan, I.H., A Handbook of EOS and ESD Models,
AMD Internal Publication (1992)
Pierce D.G., Shiley, W., Mulcahy, B., Wunder, M.,
Proceedings EOS/ESD Symposium, Anaheim, CA
(1988), p. 137–146
May, J.T., Guravage, J.F., Proceedings ISTFA, Los
Angeles, CA (1990), p. 143–147
Avery, L.R., EOS/ESD Symposium, Orlando, Florida
(1987), p. 186–191
Avery, L.R., Proceedings EOS/ESD Symposium, FL
(1987), p. 88–92
Renninger, R.G., Jon, M.C., Lin, D.L., Diep, T.,
Welsher, T.L., Proceedings EOS/ESD Symposium,
New Orleans, LA (1989), p. 59–71
Bossard, P.R., Chemelli, R.G., Unger, B.A.,
Proceedings EOS/ESD Symposium, San Diego, CA
(1980), p. 17–22
AMD Internal Publications, PLD/CQD EOS/ESD,
EOS/ESD Task Force Reports, July 1993 and January
1994
Raymond, T., Chang, K.L., Henry, Leo G., AMD 3
rd
Engineering Conference, February 1994
ESD STM5.1 — Sensitivity Testing – Human Body
Model (HBM) - Component Level
ANSI/ESD STM5.2 — Sensitivity Testing -- Machine
Model (MM) - Component Level
MIL-STD-883, Method 3015.7, March,1989
Gieser, H.A., Egger, P., Herrmann, M.R., Reiner, J.C.,
Birolini, A., ESREF Proceedings, Bordeaux, France
(1993)
Henry, Leo G., Raymond, T., Mahanpour, M., Morgan,
I., 20th International Symposium for Testing and
Failure Analysis (ISTFA), 1994
R1-2 Enhanced Particle Deposition
Attributable to Electrical Charge on a Wafer
Contributed by Douglas W. Cooper, Ph.D., The
Texwipe Company, Upper Saddle River, NJ 07458.
R1-2.1 Introduction — The presence of excess
electrical charge on a wafer can create an electrostatic
field that will lead to accelerated deposition of particles
onto the wafer. This undesirable consequence is but one
of several threats to product yield posed by the presence
of excess electrical charge on a wafer. Sections R1-1
and R1-3 of this related information discuss two other
important and potentially damaging consequences of
surface charge.
R1-2.1.1 The purpose of the discussion in this section
is to estimate the magnitude of electrostatic field that
can be tolerated before electrostatically enhanced
particle deposition becomes the dominant particle
deposition mechanism. Over the particle size range 0.01
to 0.3 µm, diffusion is the dominant, non-electrostatic
mechanism of particle deposition. Thus, values of
electrostatic fields that do not produce particle
deposition velocities greater than those attributable to
particle diffusion will be deemed tolerable. A set of
such values calculated under a specific and very
restrictive set of conditions are presented in this section.
R1-2.2 Theoretical Background — Although there are
numerous electrostatic interactions between particles
and surfaces, the dominant one is almost always the
“Coulombic” interaction: the attraction (or repulsion) of