semi合集-English.pdf - 第5004页

SEMI M15-0298 © SE MI 1989, 1998 2 18 4" Diam eter Slic es 200 400 #2, 3 7 Chips ( ≥ 0.5 mm × 0.3 mm ) None None #1 8 Cra cks None None #1 9 Dim ples None None #1, 2 10 G alliu m Inc lusions/Precipitates None None #…

SEMI M15-0298 © SEMI 1989, 19981

SEMI M15-0298

POLISHED WAFER DEFECT LIMITS TABLE FOR SEMI-INSULATING

GALLIUM ARSENIDE WAFERS

NOTE: This entire document was revised in 1998.

1 Purpose

1.1 This document defines the ma ximum number of defects, by type, that an acceptable polished Semi-Insulating

Gallium Arsenide (GaAs) wafer may exhibit.

2 Scope

2.1 This document, established sep arately from SEMI M15, in accordance with the latest requirements for the

material in advanced applications, covers polished semi-insulating GaAs wafers. The defect limits table can also be

applied to conducting GaAs wafers, except for the specification of Light Point Defects (LPD) mentioned hereinafter.

“Polished” shall refer to those wafers which have a specular chemical or chemical/mechanical finish applied to one

side of the wafer, with the backside being as cut and etched, lapped and etched, ground and etched, or polished. The

definition of defects is covered in ASTM Practices F 523 and F 154.

3 Referenced Documents

3.1 ASTM Standards

F 154 — Practices and Nomenclature for Identification of Structures and Contaminants Seen on Specular Silicon

Surfaces

F 523 — Practice for Unaided Visual Inspection of Polished Silicon Slices

Table 1 Polished Wafer Defect Limits

Item # Characteristics — Front Surface

Maximum Defects

Limits Prime Wafer

Maximum Defects

Limits Test Wafer Notes

1 Scratches

Macroscratches None #1

Maximum Number ---- 3

Maximum Length ---- Radius/2

Microscratches None Not Specified #1, 2

2Pits #1, 2

2" Diameter Slices None 5

3" Diameter Slices None 15

4" Diameter Slices None 30

3 Haze None None #1, 2

4 Cavity/Voids None None #1

5 Contamination None None #1, 2

Light Point Defects ≥ φ 2.0 µm

2" Diameter Slices 10 20 #2, 3

3" Diameter Slices 15 30 #2, 3

4" Diameter Slices 20 40 #2, 3

Light Point Defects ≥ φ 3.0 µm

2" Diameter Slices 50 100 #2, 3

3" Diameter Slices 100 200 #2, 3

1 American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohoken, PA 19428-2959

SEMI M15-0298 © SEMI 1989, 1998 2

4" Diameter Slices 200 400 #2, 3

Chips (≥ 0.5 mm × 0.3 mm)

None None #1

8 Cracks None None #1

9 Dimples None None #1, 2

10 Gallium Inclusions/Precipitates None None #1, 2

11 Orange Peel None None #1, 2

12 Saw Marks None None #1

13 Striations None None #1, 2

14 Twins None None #1, 2

Item # Characteristics – Back Surface

Maximum Defect

LimitsPrime Wafer

Maximum Defect

LimitsTest Wafer Notes

15 Stain None None #2, 4

16 Saw Marks None None #1, 5

Chips (≥ 0.5 mm × 0.3 mm)

None None #1

18 Cracks None None #1

19 Listed Defects #10, 14 None None #1, 2

20 Listed Defects #1, 2, 6 #6

NOTES:

1. These defect limits are meant to apply only to those characteristics which can be seen with the unaided eye under high-intensity illumination

according to ASTM Practice F 523. Limits for other defects listed and defined in this section which require the aid of a microscope, preferential

etching, or other apparatus must be agreed upon between supplier and user.

2. Peripheral Edge Allowance — The outer edge exclusion for observation shall be determined from the following tabe:

Diameter Outer Edge Exclusion for Observation

2 inch 2 mm

3 inch 3 mm

4 inch 3 mm

3. LPD shall be counted by measuring equipment designed for detecting laser light scatter. Selection of the measuring equipment and the

requirement for the precision are to be agreed upon between supplier and user.

4. Back Surface Stain — An area of undercutting, texturing, or oxidation, common in waxless polished wafers.

5. The depth of allowed saw marks is to be no greater than 5 µm. The measuring method is to be agreed upon between supplier and user.

6. Item #20 — To be agreed upon between supplier and user.

NOTICE: These standards do not purport to address safety issues, if any, associated with their use. It is the

responsibility of the user of these standards to establish appropriate safety and health practices and determine the

applicability of regulatory limitations prior to use. SEMI makes no warranties or representations as to the suitability

of the standards set forth herein for any particular application. The determination of the suitability of the standard is

solely the responsibility of the user. Users are cautioned to refer to manufacturer’s instructions, product labels,

product data sheets, and other relevant literature respecting any materials mentioned herein. These standards are

subject to change without notice.

The user’s attention is called to the possibility that compliance with this standard may require use of copyrighted

material or of an invention covered by patent rights. By publication of this standard, SEMI takes no position

respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this

standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and

the risk of infringement of such rights, are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

the contents in whole or in part is forbidden without express written

consent of SEMI.

SEMI M16-1103 © SEMI 1989, 2003 1

SEMI M16-1103

SPECIFICATION FOR POLYCRYSTALLINE SILICON

This specification was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the North American Silicon Wafer Committee. Current edition approved by the North

American Regional Standards Committee on September 16, 2003. Initially available at www.semi.org

October 2003; to be published November 2003. Originally published in 1989; previously published

December 1996.

NOTICE: This document was rewritten in its entirety

in 2003, and is a replacement for the previous versions

of both SEMI M16 and SEMI M16.1.

1 Purpose

1.1 This specification is intended for use in procure-

ment of polycrystalline silicon for growth of electronic

grade monocrystalline silicon ingots. Such ingots are

sliced into wafers that are subsequently used for the

production of semiconductor devices, integrated cir-

cuits, and other microelectronic components including

microelectromechanical systems (MEMS).

2 Scope

2.1 This specification covers requirements for poly-

crystalline silicon (poly) used to produce single crystal

silicon by either the modified Czochralski (Cz) or float

zone (FZ) crystal growth technique for applications in

the semiconductor device industry.

2.2 Form and dimensional characteristics are the only

standardized properties set forth below. A purchase

specification may include requirements for additional

physical properties as listed in this specification,

together with test methods suitable for determining

their magnitudes.

NOTE 1: JEITA has also established a specification for

polysilicon.

This specification also includes specification

limits and specified measurement methods for purity and

surface metal contamination. Similarities and differences

between this standard and JEITA EM-3601 are discussed in

Related Information 1.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety health practices and determine the

applicability of regulatory or other limitations prior to

use.

1 JEITA EM-3601, Standard specification for high purity

polycrystalline silicon. Available in Japanese and English from Japan

Electronics and Information Technology Industries Association, 3rd

floor, Mitsui Sumitomo Kaijo Bldg. Annex, 11, Kanda-Surugadai 3-

chome, Chiyoda-ku, Tokyo 101-0062, Japan, Web site:

www.jeita.or.jp

3 Referenced Standards

3.1 SEMI Standards

SEMI MF1708 — Practice for Evaluation of Granular

Polysilicon by Melter-Zoner Techniques

SEMI MF1723 — Practice for Evaluation of Poly-

crystalline Silicon Rods by Float-Zone Crystal Growth

and Spectroscopy

SEMI MF1724 — Test Method for Measuring Surface

Metal Contamination of Polycrystalline Silicon by Acid

Extraction-Atomic Absorption Spectroscopy

3.2 ASTM Standards

E 122 — Practice for Choice of Sample Size to

Estimate Average Quality of a Lot or Process

3.3 Other Standard

ANSI/ASQC Z1.4-1993 — Sampling Procedures and

Tables for Inspection by Attributes

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Terminology

4.1 Definitions

4.1.1 etched polysilicon — polysilicon that has been

etched with acid to remove surface contamination.

4.1.2 lot — all of the material of nominally identical

purity and characteristics contained in a single

shipment, manufactured with similar processing

conditions, and traceable to the manufacturing

conditions. A lot may be further defined as the

polysilicon produced from one reactor run.

4.1.3 polycrystalline silicon — silicon, formed by

chemical vapor deposition from a silicon source gas,

having a structure that contains large angle grain

boundaries, twin boundaries, or both. Also known as

poly, or polysilicon.

2 Volume 14.02 of the Annual Book of ASTM Standards, ASTM

International, 100 Barr Harbor Drive, West Conshohocken, PA

19428-2959, USA. Telephone: 610.832.9585, Fax: 610.832.9555,

Web site:

www.astm.org

3 American Society for Quality Control, 611 East Wisconsin

Avenue, Milwaukee, WI 53202, USA. Web site: www.asqc.org.