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SEMI M9.7-0200 © SE MI 1995, 2000 6 Figure 5 Notch Dimensions Figure 6 Character Wind o w Location NOTICE: SEMI m a kes no warranties or representations as to the suitab ility of the standards set forth herein for any pa…
SEMI M9.7-0200 © SEMI 1995, 20005
(111)Ga
Vector Normal
to Wafer Surface
(100)
Orthogonal
Misorientation
Vector Normal
to (100) Plane
_
(101)
_
(001)
_
(011)
(010)
_
_
(111)Ga
(110)
Vector Normal
to (110) Plane
Projection of Wafer Surface
Normal on (100) Plane
Projection of [110] on (100) Plane
_
(111)
As
Figure 4
Notched GaAs Wafer Illustrating Surface Orientation B, with Tilt and Orthogonal Misorientation
SEMI M9.7-0200 © SEMI 1995, 2000 6
Figure 5
Notch Dimensions
Figure 6
Character Window Location
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for
any particular application. The determination of the suitability of the standard is solely the responsibility of the user.
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the risk of infringement of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
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the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M10-1296 © SEMI 1987, 19961
SEMI M10-1296
STANDARD NOMENCLATURE FOR IDENTIFICATION OF
STRUCTURES AND FEATURES SEEN ON GALLIUM ARSENIDE
WAFERS
1 Scope
1.1 The purpose of this document is to list, illustrate,
and define various characters, features, and
contaminants that are seen on highly polished GaAs
wafers and present recommended practices for
observation of these defects. These occurrences are
frequently referred to as surface defects. The defects
and common synonyms are arranged alphabetically in
Section 4, and each structure is referred to by its most
common name and, in some cases, probably origins.
1.2 Two cases of surface preparations are considered
in this document: (1) surfaces after chemical polishing,
and (2) mechanically and chemically polished surfaces.
1.3 This standard may involve hazardous materials,
operations, and equipment. This standard does not
purport to address all the safety problems associated
with its use. It is the responsibility of whoever uses this
standard to consult and establish appropriate safety and
health practices and determine the applicability of
regulatory limitations prior to use.
2 Applicable Documents
2.1 SEMI Standard
SEMI M9 — Specifications for Round Polished
Monocrystalline Gallium Arsenide Slices
2.2 ASTM Standard
1
F 47 — Crystallographic Perfection of Silicon by
Preferential Etch Techniques
2.3 Other Standard
2
ANSI/ASQC Z1.4-1993 — Sampling Procedures and
Tables for Inspection by Attributes
3 Significance and Use
3.1 This document contains a compilation of the most
commonly observed singularly discernable structures
on polished GaAs surfaces. Ambiguities and
uncertainties regarding surface defects may be resolved
by reference to this document.
1 American Society for Testing and Materials, 100 Barr Harbor
Drive, West Conshohoken, PA 19428-2959 (The cited standard may
be found in Volume 10.05 of the Annual Book of ASTM Standards.)
2 American Society for Quality Control, 611 East Wisconsin Avenue,
Milwaukee, WI 53202
4 Definitions and Descriptions of Terms
cell structure — (block structure): Malformations
attributable to crystal inhomogeneities and that have
their origins in the crystal growth process.
chips — (edge chips, peripheral chips, peripheral
indents, surface chips): Areas of material mechanically
removed from the surface or edge of a wafer.
Chips indicate crystallographic damage in the
adjacent material. The origins of some chips are in
the handling of wafers arising from the physical
transfer or placement of the specimen for process,
measurement, or inspection purposes. The size of a
chip is defined by its maximum radial depth and
peripheral chord length as measurable on an
orthographic shadow projection of the specimen
outline.
apex chip —Any material missing from the edge of a
wafer having at least 2 distinct interior boundaries
which form one or more distinct intersections.
chuck marks — Any physical mark on either surface of
a wafer caused by a chuck or wand.
contaminant — (solvent residue, wax residue, film,
mottled surface, smudge): Surface feature that cannot
be removed by the pre-inspection (non-etching)
cleaning.
NOTE Contaminant may be foreign matter on the surface
such as localized areas which are smudged, stained,
discolored, mottled, etc., or larger areas exhibiting a hazy or
cloudy appearance resulting from a film of foreign material.
Solvent residue: type of film found on wafer
surfaces after solvent evaporation from the surface.
Note: The residue comes from either the solvent
itself or material that the solvent has removed from
the surface and redeposited. Wax residue: film of
wax that migrated onto the wafer surface from
several possible sources.
NOTE The wax originally may have been used to hold the
crystal in place during slicing or polishing. Excessive heat
used in mounting or demounting, during lapping or polishing
processes, may cause the wax to polymerize.
crack — Cleavage or fracture that extends to the surface
of a slice. It may or may not pass through the entire