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SEMI G42-0996 © SEMI 1986, 2004 1 SEMI G42-0996 (Reapproved 1104) SPECIFICATION FOR THERMAL TEST BOARD STANDARDIZATION FOR MEASURING JUNCTION-TO- AMBIENT THERMAL RESISTANCE OF SEMICONDUCTOR PACKAGES This specification wa…

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SEMI G41-87 © SEMI 1987 8
NOTICE: These standards do not purport to address
safety issues, if any, associated with their use. It is the
responsibility of the user of these standards to establish
appropriate safety and health practices and determine
the applicability of regulatory limitations prior to use.
SEMI makes no warranties or representations as to the
suitability of the standards set forth herein for any
particular application. The determination of the
suitability of the standard is solely the responsibility of
the user. Users are cautioned to refer to manufacturer’s
instructions, product labels, product data sheets, and
other relevant literature respecting any materials
mentioned herein. These standards are subject to
change without notice.
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compliance with this standard may require use of
copyrighted material or of an invention covered by
patent rights. By publication of this standard, SEMI
takes no position respecting the validity of any patent
rights or copyrights asserted in connection with any
item mentioned in this standard. Users of this standard
are expressly advised that determination of any such
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of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
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the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI G42-0996 © SEMI 1986, 2004 1
SEMI G42-0996 (Reapproved 1104)
SPECIFICATION FOR THERMAL TEST BOARD STANDARDIZATION
FOR MEASURING JUNCTION-TO-AMBIENT THERMAL RESISTANCE
OF SEMICONDUCTOR PACKAGES
This specification was technically reapproved by the Global Assembly & Packaging Committee and is the
direct responsibility of the Japanese Packaging Committee. Current edition approved by the Japanese
Regional Standards Committee on July 23, 2004. Initially available at www.semi.org September 2004; to be
published November 2004. Originally published in 1986; previously published September 1996.
1 Purpose
1.1 This document provides the requirements for a
standard thermal resistance test board to be used in
junction- to-ambient thermal resistance measurement of
a semiconductor package under still- and forced-air
condition as a referee method.
2 Scope
2.1 This document describes the thermal resistance test
board for measurement of the following packages:
• Dual-In-Line Packages (DIP),
• Plastic Chip Carrier Package (PCC),
• Quad Flat Package (QFP),
• Pin Grid Array Package (PGA), and
• Ball Grid Array Package (BGA).
2.2 This document uses SI units.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Referenced Standards
3.1 Information regarding the methods for measuring
junction-to-ambient thermal resistance, the proper
design and use of thermal test chips, and material
specifications for printed circuit boards, can be found in
the applicable documents listed below.
3.2 SEMI Standards
SEMI G32 — Guideline for Unencapsulated Thermal
Test Chip
SEMI G38 — Test Method for Still- and Forced-Air
Junction-to-Ambient Thermal Resistance
Measurements of Integrated Circuit Packages
3.3 Military Specifications
1
MIL-P-13949 — Material Specification for NEMA
Grade G-10 Printed Circuit Board Material
MIL-STD-883C — Method 1012.1, Thermal
Characteristics
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
4 Terminology
4.1 Definitions
4.1.1 junction temperature,T
J
— in degrees Celsius is
used to denote the temperature of the semiconductor
junction in the microcircuit in which the major part of
the heat is generated. Usually the measured junction
temperature is only indicative of the temperature in the
immediate vicinity of the element used to sense the
temperature.
4.1.2 junction-to-ambient thermal resistance, R
θJA
—
in degrees Celsius/watt is the temperature difference
between the junction and the ambient, divided by the
power dissipation P
H
.
4.1.3 power dissipation, P
H
— in watts is the heating
power applied to the device causing a junction-to-
reference point temperature difference.
4.1.4 temperature sensitive parameter, TSP — is the
temperature dependent electrical characteristic of the
junction under test which can be calibrated with respect
to temperature and subsequently used to detect the
junction temperature of interest.
5 Ordering Information
5.1 The material required for making the thermal test
board can be ordered through any electronic supply
store.
1 United States Military Standards, Available through the Naval
Publications and Forms Center, 5801 Tabor Avenue, Philadelphia,
PA 19120-5099, USA. Telephone: 215.697.3321
SEMI G42-0996 © SEMI 1986, 2004 2
6 Requirements
6.1 General requirements regarding the materials used
for test board, the specified physical dimensions of the
test board and other necessary conditions are described
in the following paragraphs:
6.1.1 Material Requirements
6.1.1.1 The test board material should be NEMA Grade
G-10 or equivalent.
6.1.1.2 The conductor traces on the board must be
copper and the total amount of copper should not
exceed 20% of the surface area of the board.
6.1.1.3 The vias should be plated through.
6.1.1.4 External wire connections from the package
leads to edge connector leads must be made with 24-
gauge copper wire.
6.1.2 Thermal Test Board Physical Dimensions and
Layout — Five separate boards are designed for the
purpose of thermal measurements of different types of
semiconductor packages.
6.1.2.1 Physical Dimensions
6.1.2.1.1 Length — 114.3 mm ± 0.254 (4.50 inches ±
0.01)
6.1.2.1.2 Width — 76.2 mm ± 0.254 (3.00 inches ±
0.01)
6.1.2.1.3 Thickness — 1.524 – 1.651 mm ± 0.127 mm
(0.060 – 0.065 inches ± 0.005 inches)
6.1.2.2 Layout
6.1.2.2.1 Dual-in-Line Packages or Sockets (See
Figure 1.)
a. The vias shall be located on 2.54 mm (0.10 inch)
centers ± 0.076 mm (0.003 inches) non-
accumulative.
b. The diameter of the vias shall be 1.143 mm (0.045
inches) ± 0.076 mm (0.003 inches).
c. The location of the vias on the board shall be as
shown in Figure 1.
6.1.2.2.2 Chip Carrier Packages (See Figure 2.)
a. The copper traces shall be laid out on the PC board
as shown in Figure 2. The traces are drawn on 1.27
mm (0.050 inch) centers ± 0.127 mm (0.005 inch)
non-accumulative.
b. The vias at the end of the copper traces shall be
located on the 2.54 mm (0.10 inch) centers ± 0.076
mm (0.003 inch) non-accumulative.
6.1.2.2.3 Quad Flat Packages (0.3, 0.4, 0.5, and 0.65
mm lead pitch) or sockets (See Figures 3–6.)
a. The copper traces shall be laid out on the PC board
as shown in Figures 3–6. The traces are drawn in
accordance with pitch and width as shown in Table
1.
Table 1 Trace Pitch and Width for QFP Package
Boards
Package Lead Pitch
(mm)
Trace Pitch (mm)
Trace Width (mm)
0.65 0.65 ± 0.05 0.35
0.5 0.5 ± 0.05 0.25
0.4 0.4 ± 0.04 0.2
0.3 0.3 ± 0.03 0.15
6.1.2.2.4 Pin Grid Array Packages or Sockets (See
Figure 7.)
a. The vias shall be located on 2.54 mm (0.10 inch)
centers ± 0.076 mm (0.003 inches) non-
accumulative.
b. The diameter of the copper lead shall be 1.2 mm ±
0.046 mm and the hole shall be 0.95 mm ± 0.046
mm.
c. The location of the vias on the board shall be as
shown in Figure 7-1.
6.1.2.2.5 Ball Grid Array Packages (1.5, 1.27, and 1.0
mm Ball Pitch) (See Figure 8.)
a. The copper traces shall be laid out on the PC board
as shown in Figure 8-1. The traces and vias are
drawn in accordance with configuration and
dimension as shown in Table 2.
b. The board shall be covered by resist as shown in
Figure 8-2. The back side of the board shall not be
covered by resist.