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SEMI M11-0704 © SEMI 1988, 2004 17 10.2 The wafers supplied under this specification shall be ide ntified by appropriately labeling the outside of each box or container and each subdi vision thereof in which it may reaso…

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SEMI M11-0704 © SEMI 1988, 2004 16
Table 1 IC Epitaxial Wafers - Basic Surface Criteria
Item Characteristics
Maximum
Acceptability Limits
Test Method
Notes and Reference
Documents
1 Stacking Faults 1 per cm
2
SEMI MF1726 1
2 Slip None SEMI MF523 or SEMI MF1726 1, 5, 6
3 Dislocations None SEMI MF1726 1
4 Total Localized
Light Scatterers
2000 per m
2
! 0.5 µm LSE, based on calibration of
surface scanning inspection systems with
latex spheres, 90% capture rate
1, 7
Table 2
5 Haze None SEMI MF523 Section 12.2 4, 7
6 Scratches None SEMI MF523 Section 12.2 2, 7
7 Edge Chips None SEMI MF523 Section 12.2
8 Foreign Matter None SEMI MF523 Section 12.3 4
9 Back Surface
Contamination
None SEMI MF523 Section 12.4 4
NOTE 1: Defect limits shall apply to quality area, which is defined as the entire wafer surface except a defined outer annulus of 4 mm and any
area included in a window where there is a laser identification mark.
NOTE 2: The cumulative AQL for both front surface and back surface of wafer is 2.5.
NOTE 3: The cumulative AQL for both front surface and back surface of wafer is 1.0.
NOTE 4: Any adherent contaminants, such as stains, glovemarks, dirt, smudges, warps, and solvent residues. This characteristic does not include
point defects. Any nonadherent contamination or particulate matter easily removed by industry-accepted cleaning techniques shall not constitute
foreign matter or haze.
NOTE 5: Test method(s) to be agreed upon between supplier and purchaser.
NOTE 6: For observation of gross slip, examine the epitaxial layer under illumination conditions specified in Section 12.2 of SEMI MF523. For
more demanding applications, it may be desirable to etch the surface in accordance with SEMI MF1726.
NOTE 7: In today’s technology, it may be possible to do this inspection using automated laser scanning systems; however, a standard test
procedure has yet to be developed. Application of automated inspection must be agreed upon between supplier and user.
8 Sampling
8.1 Unless otherwise specified, appropriate sample
sizes shall be selected from each lot according to
ANSI/ASQC Z1.4-1993. Quality characteristics shall
be assigned an acceptable quality level (AQL) in
accordance with ANSI/ASQC Z1.4-1993. Inspection
levels shall be agreed upon between supplier and
purchaser. Accept and reject criteria are to be based on
defective wafers, not on defective characteristics.
8.2 Unless otherwise specified, the following AQL’s
shall be assigned:
8.2.1 Epitaxial Layer Center-point Thickness and
Variation, 1%;
8.2.2 Epitaxial Layer Center Net Carrier Density and
Variation, 1%;
8.2.3 Epitaxial Wafer Defects, Cumulative, 2.5%.
9 Certification
9.1 Upon request of the purchaser in the contract or
order, a manufacturer’s or supplier’s certification that
the material was manufactured and tested in accordance
with this specification, together with a report of the test
results, shall be furnished at the time of shipment.
9.2 The supplier and purchaser may agree that the
material shall be certified as “capable of meeting”
certain requirements. In this context, “capable of
meeting” shall signify that the supplier is not required
to perform the appropriate tests in Section 7; however,
if the purchaser performs the test and the material fails
to meet the requirement, the material may be subject to
rejection.
10 Packing and Marking
10.1 Special packing requirements shall be subject to
agreement between the supplier and the purchaser.
Otherwise all wafers shall be handled, inspected, and
packed in such a manner as to avoid chipping,
scratches, and contamination, and in accordance with
the best industry practices to provide protection against
damage during shipment.
SEMI M11-0704 © SEMI 1988, 2004 17
10.2 The wafers supplied under this specification shall be identified by appropriately labeling the outside of each
box or container and each subdivision thereof in which it may reasonably be expected that the wafers will be stored
prior to further processing. Identification shall include supplier’s name and reference number, purchaser’s p.o.
number, quantity, dopant, orientation, conductivity type of substrates and epitaxial layers, carrier density, and
thickness of the epitaxial layer. The reference number assigned by the supplier shall provide ready access to
information concerning the fabrication history of the particular wafers in that lot. Such information shall be retained
on file at the manufacturer’s facility for at least one year after that particular lot has been shipped.
11 Guides
11.1 The specifications in the epitaxial guides are examples which were formed by a consensus of viewpoints. They
may or may not be used as a foundation to specify an epitaxial wafer for use in device manufacture. Their usefulness
can be increased by considering the guides prior to developing a device design or process. The required specification
is deter-mined by the device and the process design, the guides are suggestions from which a specification can
evolve.
11.2 An epitaxial guide can be viewed as a generic epitaxial wafer specification or as an example of a specification.
These tables provide common epitaxial wafer characteristics which describe starting wafers useful for the
manufacture of some twin tub CMOS devices.
11.3 The guides in Tables 3, 4, 5, 6, 7, 8, 9, and 10 provide a series of options intended to increase the awareness of
epitaxial specifications and to provide information from which a specification can be formulated.
11.4 SEMI M18 was used as a template for formulating these tables. When suitable to the application, the guides
can be used intact, reducing the proliferation of specifications and formats.
11.4.1 Table 3 is representative of 1.0 µm design rule epitaxial wafer criteria.
11.4.2 Table 4 is typical of an epitaxial wafer criteria for custom twin tub CMOS, 0.35 µm design rule devices, such
as, but not limited to ASIC’s, FPGA’s, linears, DSP’s, and microprocessors.
11.4.3 Table 5 is typical of an epitaxial wafer criteria for 0.35 µm design rule devices such as 64 megabit DRAM’s.
11.4.4 Table 6 is typical of epitaxial wafer criteria for twin tub CMOS, 0.25 µm design rule devices, such as, but
not limited to ASIC’s, FPGA’s, linears, DSP’s, and microprocessors.
11.4.5 Table 7 is typical of epitaxial wafer criteria for twin tub CMOS, 0.18 µm design rule devices.
11.4.6 Table 8 is typical of epitaxial wafer substrate criteria for a wafer pre-epitaxial that will be used in twin tub
CMOS, 0.25 µm design rule devices.
11.4.7 Table 9 is typical of epi wafer criteria for twin tub CMOS, 0.13 µm design rule devices.
11.4.8 Table 10 is typical of epi wafer criteria that can be used to develop a wafer specification for 90 nm Design
Rule CMOS devices.
Table 2 Equivalent Units for Localized Light Scatterers
Diameter
1
100 125 150 200 300 Density
per m
2
Localized Light Scatterers per Wafer
Density
per cm
2
100 1 1 2 3 7 0.01
200 1 2 3 6 13 0.02
300 2 3 5 9 20 0.03
400 3 4 6 12 27 0.04
500 3 5 8 14 33 0.05
600 4 6 10 17 40 0.06
700 5 8 11 20 47 0.07
800 5 9 13 23 54 0.08
SEMI M11-0704 © SEMI 1988, 2004 18
Diameter
1
100 125 150 200 300 Density
per m
2
Localized Light Scatterers per Wafer
Density
per cm
2
900 6 10 14 26 60 0.09
1000 7 11 16 29 67 0.10
1100 7 12 17 32 74 0.11
1200 8 13 19 35 80 0.12
1300 9 14 21 38 87 0.13
1400 9 15 22 41 94 0.14
1500 10 16 24 43 100 0.15
1600 11 17 25 46 107 0.16
1700 11 18 27 49 114 0.17
1800 12 19 29 52 121 0.18
1900 13 20 30 55 127 0.19
2000 13 22 32 58 134 0.20
2100 14 23 33 61 141 0.21
2200 15 24 35 64 147 0.22
2300 15 25 36 67 154 0.23
2400 16 26 38 69 161 0.24
2500 17 27 40 72 167 0.25
2600 17 28 41 75 174 0.26
2700 18 29 43 78 181 0.27
2800 19 30 44 81 188 0.28
2900 19 31 46 84 194 0.29
3000 20 32 48 87 201 0.30
3100 21 33 49 90 208 0.31
3200 21 34 51 93 214 0.32
3300 22 35 52 96 221 0.33
3400 23 37 54 98 228 0.34
3500 23 38 55 101 234 0.35
3600 24 39 57 104 241 0.36
3700 25 40 59 107 248 0.37
3800 25 41 60 110 254 0.38
3900 26 42 62 113 261 0.39
4000 27 43 63 116 268 0.40
4100 27 44 65 119 275 0.41
4200 28 45 67 122 281 0.42
4300 29 46 68 124 288 0.43
4400 29 47 70 127 295 0.44
4500 30 48 71 130 301 0.45
4600 31 49 73 133 308 0.46
4700 31 51 74 136 315 0.47
4800 32 52 76 139 321 0.48
4900 33 53 78 142 328 0.49
5000 33 54 79 145 335 0.50