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SEMI G61-94 © SEMI 1994 2 3 Definition of Terms 3.1 bl ister (bubble) ceramic — an e nclo sed, localized separation within or bet ween the layers of a ceramic package that does not expose an underlying la yer of ceramic …
SEMI G61-94 © SEMI 19941
SEMI G61-94
SPECIFICATION FOR COFIRED CERAMIC PACKAGES
1 Preface
1.1 Purpose — This specification defines the materials
and acceptance criteria for high-temperature, cofired
ceramic packages.
1.2 Scope — The criteria detailed in this specifiication
apply to the following package outlines registered with,
or specified by JEDEC (see Publication 95), EIAJ, or
MIL-STD-1835 specifications:
Chip Carriers (Leadless or Leaded)
Dual-in-Line Packages (Sidebrazed)
Flat Packs (Top or Bottom Brazed)
Grid Arrays (Land/Ball or Pin)
NOTE 1: Packages not meeting these specifications may also
use the criteria as appropriate.
This document consolidates the criteria for all cofired
packages so that package amnufacturing and inspection
may be simplified and costs reduced.
1.3 Units — U.S. Customary (inch -pound) or metric
(SI) units may be used at the customer’s discretion.
This specification uses U.S. Customary units as the
prime unit. In the drawings, only U.S. Customary units
are detailed.
2 Applicable Documents
2.1 Order of Precedence — To avoid conflicts, the
order of precedence when ordering packages shall be as
follows:
Purchase Order
Customer’s Package Drawings
This Specification
Reference Documents
Related Documents
2.2 Referenced Documents
2.2.1 SEMI Specifications
SEMI G6 — Seal Ring Flatness
SEMI G8 — Gold Plating — Temperature Resistance
SEMI G23 — Measuring the Inductance of Package
Leads
SEMI G24 — Measuring the Lead-to-Lead and Loading
Capacitance of Package Leads
SEMI G25 — Measuring the Resistance of Package
Leads
SEMI G30 — Test Method, Junction-to-Case Thermal
Resistance Measurements on Ceramic Packages
SEMI G35 — Test Methods for Lead Finishes on
Semiconductor (Acitve) Devices
2.2.2 ANSI Specifications
1
ANSI Y14.5M — Dimensioning and Tolerancing
2.2.3 ASTM Specifications
2
ASTM B 568 — Measurement of Coating Thickness by
X-Ray Spectrometry
ASTM E 18 — Test Methods for Rockwell Hardness
and Rockwell Superficial Hardness of Metallic
Materials
ASTM E 165 — Liquid Penetrant Inspection Method
ASTM E 384 — Test Method for Microhardness of
Materials
ASTM F 109 — Surface Imperfections on Ceramics
2.2.4 JEDEC Specifications
3
Pub. No. 95 — Registered and Standard Outlines for
Semiconductor Devices
2.2.5 Military and Federal Specifications
4
MIL-STD-7883 — Brazing
MIL-STD-38510 — General Spec. for Microcircuits
MIL-G-45204 — Gold Plating — Electrodeposited
QQ-N-290A — Nickel Plating (Electrodeposited)
2.2.6 EIAJ Specifications
2.3 Related Documents
2.3.1 Military and Federal Specifications
MIL-STD-105 — Sampling Procedures and Tables for
Inspection by Attributes
1 ANSI, 1430 Broadway, New York, NY 10018
2 American Society of Testing Materials, 100 Barr Harbor Drive,
West Conshohoken, PA 19428-2959
3 JEDEC, 2001 Eye Street N.W., Washington D.C. 20006
4 Military Standards, Naval Publications and Form Center, 5801
Tabor Avenue, Philadelphia, PA 19120
SEMI G61-94 © SEMI 1994 2
3 Definition of Terms
3.1 blister (bubble) ceramic — an enclosed, localized
separation within or between the layers of a ceramic
package that does not expose an underlying layer of
ceramic or metallization.
3.2 blister (bubble) metallization — an enclosed,
localized separation of a metallization layer from its
base material (such as ceramic or another metal layer)
that does not expose the underlying layer.
3.3 braze — in semiconductor pac kages, an alloy used
to attach pins, leads, seal rings and heat sinks/studs to
the package.
3.4 burr — an adherent fragment of parent material at
a component edge. In leadframes, the metal burr, due to
the stamping operation, may be in the horizontal or
vertical direction to the surface. In ceramic packages,
this type of characteristic is called a fin.
3.5 castellations — metallized sem i-circular channels
on chip carrier edges which provide contact between
internal package metallization traces and the external
test pads. These castellations provide for improved
solder fillets during attachment to a circuit board (see
Figure 1).
3.6 cavity-down packages — packages where the die
surface faces the mounting board. (See Figure 2 for the
pin grid array packages in the cavity-down
configuration. It is more usual to refer to the chip
carrier mounting surfaces as the seating planes. In this
cavity orientation, the seating plane is Seating Plane 2
per JEDEC JC-11.)
3.7 cavity-up packages — package s where the die
surface faces away from the mounting board (see
Figure 2 or Seating Plane 1 for chip carriers).
3.8 chip — region of material mis sing from a
component (e.g., ceramic from a package, or solder
from a preform). The region does not progress
completely through the component and is formed after
the component is manufactured. Chip size is defined by
its length, width and depth from a projection of the
design platform. Also called chipout (see Figure 1).
3.9 co-fired — in the manufacturing of some types of
ceramic packages, the technology used to join together
various ceramic layers and metallization patterns
screened onto those layers by simultaneous firing at
high temperature.
3.10 contact pad — in a leadless ch ip carrier or land
grid array, the metallized areas on the bottom of the
package that provide contact point between the internal
leads and connecting external circuitry. They are also
used for electrical test pads.
3.11 crack — a cleavage or fracture that extends to the
surface of a semiconductor package or solder preform.
The crack may or may not pass through the entire
thickness of the package or preform.
3.12 critical seal area (ceramic) — on a
semiconductor package, the area bounded by the
shortest nominal design distance from the largest
cavity, usually the wire bond cavity, to the edge of the
package or ceramic layer forming the seal area.
3.13 critical seal area — metallizat ion or metal ring
— The entire area of the seal ring; it applies to plated
refractory metal or a metal ring.
3.14 critical seal path (ceramic) — on a
semiconductor package, the shortest nominal design
distance from the largest cavity, usually the wire bond
cavity, to the edge of the package or ceramic layer
forming the seal area.
3.15 delamination — in a co-fired ceramic package,
chip carrier, pin grid array, etc., the separation of one
ceramic layer from another.
3.16 element (packaging) — part of a semiconductor
package feature (e.g., package leads have braze
paddle/stand-off and contact elements, pins have the
nail head/braze area and contact elements).
3.17 fin — on a ceramic package or cap, a fine
feathery-edged projection of parent ceramic material on
the corner of the ceramic body.
3.18 flatness — in a ceramic package or leadframe,
the allowable deviation of a surface from a defined
reference plane. The tolerance zone is defined by two
parallel planes within which the surface must lie.
3.19 foreign material — an adheren t particle that is
not parent material of the component. Adherence means
that the particle cannot be removed by an air or nitrogen
blast at 20 psi.
3.20 heat exchange area — a metal lized region on one
major surface of the package to which heat sinks may
be attached by brazing, soldering, or adhesive resin.
3.21 layer — on a cofired ceramic package, the body
is made from layers of ceramic or metallized ceramic.
The layers are defined by their functionality, and
several ceramic layers may be described as comprising
one functional layer if all are common in plan-form and
function (e.g., die attach cavity) (see Figure 4).
3.22 lead offset — in brazed lead ceramic packages,
the variation in position of the centerline of the lead
with reference to the centerline of the braze pad to
which it is mounted.
3.23 lead sweep — lead movement, measured with
respect to a datum, perpendicular to the top or bottom
SEMI G61-94 © SEMI 19943
of the package that passes through the designed mid-
point of the lead where the lead is attached to the
package (e.g., side-brazed laminates), or where the lead
exits the package body (e.g., plastic dual-in-line
packages). The movement is viewed from the side of
the package, not the ends.
3.24 lead-to-lead separation — the distance between
adjacent leads when measured from their centerlines at
the point of connection to the package.
3.25 lead tweeze — lead movement , measured with
respect to a datum, perpendicular to the top or bottom
of the package that passes through the designed mid-
point of the lead where the lead is attached to the
package (e.g., side-brazed laminates), or where the lead
exits the package body (e.g., plastic dual-in-line
packages). The movement is viewed from the ends of
the package, not the side and the lead movement is
from the edges of the package in toward the centerline
of the package.
3.26 metallization void — the absence of a clad,
evaporated, plated or screen-printed metal layer or
braze from a designated area. Also called metal or
plating void.
3.27 peeling (flaking) — any separation of a plated,
vacuum-deposited, or clad metal layer from the base
metal of a leadframe, pin heatsink, or seal ring, from an
underplate, or from a refractory metal on a ceramic
package. Peeling exposes the underlying metal.
3.28 pin offset — the variation in po sition from the
centerline of the pin to the centerline of the braze pad to
which it is mounted.
3.29 pin sweep — pin movement, measured with
respect to a datum, perpendicular to the top or bottom
of the package that passes through the designed mid-
point of pin where the pin is attached to the package
(e.g., pin grid arrays). The movement is viewed form
the side of the package, not the ends.
3.30 pin-to-pin separation — the distance between
adjacent pins when measured from their centerlines at
the point of connection to the package.
3.31 pin tweeze — pin movement, m easured with
respect to a datum, perpendicular to the top or bottom
of the package that passes through the designed mid-
point of pin where the pin is attached to the package
(e.g., pin grid arrays). The movement is viewed form
the ends of the package, not the side and the pin
movement is from the edges of the package in toward
the centerline of the package.
3.32 pit — in semiconductor packa ges, plastic or
ceramic, or in the leadframes, a shallow depression or
crater. The bottom of the depression must be visible in
order for the term to apply. A pit is formed during
component manufacture (see Figure 3).
3.33 porous surface — an uncompa cted ceramic
surface often showing fine pits.
3.34 projection — on a semiconduc tor package
(plastic or ceramic), leadframe or preform, and
irregularly raised portion of a surface indigenous to the
parent material.
3.35 pullback — on a semiconducto r package, the
linear distance between the edge of a cavity cut into a
ceramic layer and the first measurable glass or
metallization layer interface coated onto the top surface
of that layer. The total pullback may be the result of the
high temperature processing required to manufacture
the package or to coat the surface. It may also be the
result of design considerations (see Figure 5).
3.36 rundown — on a semiconductor package, the
linear distance from the upper surface of a ceramic
cavity layer to the bottom point of the overhang into the
cavity, of a sealing glass or metallization layer that has
been screened onto that surface (see Figure 5).
3.37 scrape — the irregular removal of a deposited
layer from a base material by a shearing action from
another surface such that the base material is exposed
over an extended area. It can also apply to the removal
of surface layers from a material. The material removed
from the scraped area may build up at the edges of the
scrape. The deposited layer may be a metal or glass.
3.38 seal area — on a semiconductor package, the
area designated for sealing a cover or lid to a cofired
ceramic package, or a cap to a cer-DIP or cer-pack
base. In the case of a co-fired ceramic package the seal
area may be either bare ceramic for glass sealing or a
metallized area for solder sealing. The metallized seal
area may be a plating over refractory metallization or a
metal ring, usually iron-nickel-cobalt or iron-nickel
alloys, brazed to the refractory metal.
3.39 seating plane — in plug-in pac kages such as
dual-in-line (side-brazed or cer-DIP) or pin grid arrays,
the plane defined by the three lowest stand-off features
on the lead or pins as measured from the bottom of the
package, or in the absence of these features, by the
package base or mounting plane (see Figure 6). The
features, such as shoulders or projections, hold the
package off the circuit board to which it is mounted.
This gap allows solder flux and residues to be cleaned
after soldering the device and, in some cases, to allow
for sufficient cooling air flow around the device. A
prescribed force is used to hold the device in the
mounting holes when the seating plane is to be
measured.