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SEMI M60-0305 © SEMI 2005 6 5.4.2 Stress Current Density — For reliable measurement, a voltage/curre nt source with a stable output wa ve shape shall be used. It is n ecessary to stabilize the output as much as possible.…
SEMI M60-0305 © SEMI 2005 5
density will give us the approximate failure rate by the A-B mode breakdown. It is necessary to determine the
classification of failure modes in advance. This is because reliabilities depend on the devices fabricated on the
Si wafer (electrode material, gate oxide thickness, operating voltage, etc.). Refer to an example of mode
classification described in Figure RI-2.
4.2.3.4 Time Zero Dielectric Breakdown (TZDB) — one of the dielectric breakdown characteristic of the gate oxide.
4.2.3.4.1 Discussion — To measure TZDB, oxide leakage current is monitored with an electric field applied to the
MOS capacitor stepwise from 0 to 15MV/cm (for example in the case of a 25 nm-thick oxide, actual applied voltage
would be from 0 to 37.5V). The electrode is negatively biased so that the Si surface is in accumulation and the
electric field is applied effectively. Applied electric field (or voltage) is measured when the oxide leakage current
reaches a predetermined value (judgment current), in other words when the gate oxide breaks down. The influence
of COPs on gate oxide breakdown can be estimated from the distribution of breakdown electric field.
5 Summary of Method
5.1 Overview — This test method consists of two parts. The first one is the fabrication of a number of similar MOS
capacitors on silicon wafers, and the second one is the measurement of the electric charge injected just before the
dielectric breakdown of the MOS capacitors. To measure the injected electric charge, the voltage applied to a MOS
capacitor is controlled so that the current is kept constant. The voltage is monitored throughout the test, and the time
from the beginning to a sudden voltage drop which results from the dielectric breakdown of the silicon dioxide film
is measured. The injected electric charge is the product of the measured time and the gate current density.
5.2 MOS Capacitor Fabrication Process — Many MOS capacitors are formed on the test wafer. The MOS
fabrication process consists of wafer cleaning, thermal oxidation, poly-Si deposition, phosphorous doping, activation
heat treatment, photolithography and etching, in the case of using poly-Si electrodes. The details of the MOS
capacitor fabrication process are shown in SEMI M51. When materials other than poly-silicon are used for
electrodes, the process shall be adjusted to the material used. Although thermally grown 20–25 nm-thick gate oxide
films are recommended in SEMI M51, oxide films as thin as 10 nm can be used depending on the situation.
However, measurement shall be performed carefully for oxide films thinner than 3 nm, because breakdown
judgment becomes difficult under the influence of direct tunneling current. See SEMI C3.6, SEMI C3.54, SEMI
C21, SEMI C27, SEMI C28, SEMI C30, SEMI C35, SEMI C38, SEMI C41, SEMI C44, SEMI C54, SEMI C59.
5.3 Fabrication Environment — It is necessary to fabricate MOS capacitors in a clean room environment of 1000 or
better class in total quality. That is, it needs to be confirmed that the A mode failure rate is 10% or less by TZDB
evaluation. The A mode failure depends not only on the particle of work environment atmosphere but also on the
ultrapure water, fixtures, process apparatus, clean clothes, operation rules etc. Heavily contamination such as
alkaline or heavy metal has an important negative effect on the GOI of the oxide.
5.4 Measurement of Electric Characteristic of MOS Capacitors
5.4.1 The dielectric breakdown defect density of the silicon oxide film is evaluated by constant current TDDB
measurement of the MOS capacitors. The evaluation consists of the measurement of charge injected before the
dielectric breakdown of the MOS capacitors. To measure the injected charge, voltage applied to a MOS capacitor is
controlled so that the current is kept constant. The applied voltage is monitored throughout the test, and the time to
sudden voltage drop which results from dielectric breakdown of the silicon dioxide film is measured. The amount of
the injected charge is the product of the measured time and gate current density. The defect density of the oxide
film is evaluated from the Weibull plot (cumulative failure rate) of the dielectric breakdown data of approximately
100 MOS capacitors.
SEMI M60-0305 © SEMI 2005 6
5.4.2 Stress Current Density — For reliable measurement, a voltage/current source with a stable output wave shape
shall be used. It is necessary to stabilize the output as much as possible. In the constant current TDDB
measurement, a constant current is continuously applied, and voltage is monitored. The dielectric breakdown is
judged by a sudden drop in the voltage monitored. If the applied stress current density is too low, the time to
breakdown will be too long to be realistic. Contrarily, too a high current density is also unsuitable because the
voltage drop in the oxide breakdown instant becomes small. Considering these factors, the recommended stress
current density range is from 0.01 to 0.1A/cm
2
.
5.5 Measurement Temperature — Besides current density, the measurement temperature is also an important
parameter which determines measurement time. It is appropriate to measure in the temperature range of room
temperature to 150ºC, taking into consideration the temperature tolerance of the measurement equipment. In
addition, there are cases that since silicon wafer, stage chuck, probe, and so on, expand at a high temperature, the
probe deviates from the predetermined position, thus consideration is required when selecting probing machines.
5.6 Breakdown Judgment — To measure the dielectric breakdown lifetime of an oxide film, the voltage applied to a
MOS capacitor is controlled so that a current is kept constant. The applied voltage is monitored throughout the test.
The dielectric breakdown of the oxide is judged by sudden voltage drop. In practice, at the dielectric breakdown the
applied voltage becomes lower than the criterion voltage defined before. The dielectric breakdown lifetime is the
stress application time till breakdown. If the criterion voltage is too low, it can easily affected by noise. In contrast,
the chance of missing breakdown events is increased if the criterion voltage is too high. The changes in two
continuous measured gate voltages can be used to judge the oxide breakdown. The instant at which the voltage
change became larger than the criterion value is defined as dielectric breakdown. The same caution mentioned
above is also required in this case. In this round robin, the current density is from 0.01 to 0.1A/cm
2
, the sheet
resistance of the poly-silicon electrode is approximately 50 ohm/sq, gate electrode area is from 1mm
2
to 10mm
2
,
gate oxide thickness is 25nm and measurement temperature is from room temperature to 150ºC. In this case
dielectric breakdown is determined from the changes in two continuous measured gate voltages. For example, the
change in gate voltage is larger than X
criterion
(%) of the former gate voltage value. X
criterion
is higher than 10%.
Alternatively, dielectric breakdown is determined with the measured electric field, E
ox
. It is considered that
dielectric breakdown does not happen until E
ox
becomes E
criterion
or lower. E
criterion
is higher than 4MV/cm. Stable
measurement results are obtained in both cases. Of course, these criterion electric fields depend on gate oxide
thickness, sheet resistance and area of gate electrode, stress current, stress temperature, and so on. To detect the
dielectric breakdown with the change in gate voltage as shown in Figure 2, it is desirable to determine the criterion
under each condition in advance.
5.7 Estimation of Accidental Failure Rate — As mentioned before, the total number of A-A and A-B mode failures
is related to the crystal quality of the mirror polished CZ Si wafers. It takes a long time to measure the wearout
lifetime of all the MOS capacitors. If a requirement is only measurement of the accidental failure rates of the MOS
capacitors on silicon wafer surface, TDDB measurement can be finished without detecting the wearout lifetimes.
That is, maximum stress time, T
max
, is determined to be Q
bd
in the A-B mode range in advance. The cumulative
failure rate at T
max
is the total failure rate of the A-A and A-B modes. If the rough shapes of the Weibull plots of the
TDDB measurement can be predicted in advance, T
max
shall be determined as to be the maximum Q
bd
in the
relatively flat range of the A-B mode. This reason is that variation of T
max
has little influence on the evaluation of
total accidental failure rates. This method has an advantage of that the failure rate of the A-A and A-B modes is
evaluated very quickly.
5.8 Constant-Voltage TDDB — The constant-voltage TDDB method is also used for a lifetime test. Measurement
conditions shall be optimized for each purpose. For TDDB, an average electric field of approximately 10MV/cm is
required. Therefore, the effective electric field applied to an oxide film is influenced by a series resistance. Thus,
the constant current TDDB is more suitable.
SEMI M60-0305 © SEMI 2005 7
Drop of applied
gate voltage at
breakdown
Breakdown judgement
voltage level
Applied Gate Voltage (V)
Time (sec)
Drop of applied
gate voltage at
breakdown
Breakdown judgement
voltage level
Applied Gate Voltage (V)
Time (sec)
NOTE: A typical applied gate voltage as a function of stress time and a relationship between a drop of the applied gate voltage at
dielectric break-down and breakdown judgment voltage level.
Figure 2
6 Significance and Use
6.1 This standard gives the procedure for characterizing mirror-polished, p-type CZ silicon wafers using the
dielectric breakdown defect densities of the gate oxide thermally grown on them. The MOS capacitors shall be
formed in accordance with the fabrication processes described in §5 and SEMI M51. This reason is because the
oxide characteristics depend on the fabrication processes. If MOS capacitors would be formed with different
fabrication processes, it is desirable to confirm that these GOI results are similar to those of the MOS capacitors
formed by the fabrication processes described above. Particularly, the electrode material of the MOS capacitors has
a great influence on the dielectric breakdown of the gate oxide. Poly-silicon is specified as the electrode material in
this standard. The test with the poly-silicon gate electrode gives us the test results directly applicable to the wafers
for the integrated circuits rather than other metal electrodes, because poly-silicon electrodes are commonly used in
actual devices. Of course other materials are also available for electrodes. Where other electrode material is used,
an appropriate method for each case and the correlation data between poly-silicon and the other material shall be
prepared.
6.2 It is well known that both the silicon surface morphology and the cross-sectional structure at the pattern edge of
the active region of the MOS devices influence the dielectric breakdown of the gate oxide. Various types of
contaminants also influence the dielectric breakdown of the gate oxide. The extent of contamination by alkaline
metals, heavy metals or organic particles increases, as the sample fabrication process progresses.
6.2.1 The electrode area and total number of MOS capacitors shall be chosen to be suitable for the purpose of the
test. The suitable gate area for the constant current TDDB measurement depends on the applied stress (i.e. induced
current). If the gate electrode area is too large, parasitic resistance of the gate electrode disturbs uniform application
of stress current to gate oxide. That is, too a high current density leads to nonuniform stress on gate oxide. As a
result, the reliability of the measurement is reduced. The gate oxide with a defect density is able to be evaluated
using two sets of MOS capacitors. Although the gate area and total number of MOS capacitors have the same
product, one set consists of many capacitors with a small gate area and the other set consists of a few of capacitors
with a large gate area. The TDDB evaluations using the former are more desirable than those using the latter. In
this round robin, where a polycrystalline silicon thickness is 300 nm, sheet resistance is 50/ and gate area is
smaller than 5 mm
2
, reasonable TDDB results were obtained.
7 Interferences
7.1 Since this is a DC measurement, care must be taken to make sure that the silicon wafer has a low-resistance
ohmic contact. There must be no dielectric film on the back surface, e.g., silicon oxide, in order to effectively apply
a voltage bias to the gate oxide. It is not necessary for this to be carried out with a metallic contact on the back
surface of the wafer under test. However, when the vacuum chucking is weak, care must be taken because of the
possibility that the dielectric breakdown of the gate oxide is not accurately judged due to an increase in parasitic
resistance. It is strongly suggested that testing be carried out with a current polarity such that the silicon surface will
be in accumulation below the gate oxide, that is, negative voltages for p-type silicon wafers. If the polarity of the
voltage is chosen to be in the reverse direction, the breakdown voltage may not be accurately measured due to the
presence of a depletion layer below the gate oxide. Controls of electrical noise in this test method are crucial to the