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SEMI MF1771-0304 © SEMI 2003, 2004 2 issues, it is widely felt that failure to continu e oxide breakdown t esting to the po int of catastro phic oxide failure may mask the presence of defect tails, which are of critical …
SEMI MF1771-0304 © SEMI 2003, 2004 1
SEMI MF1771-0304
TEST METHOD FOR EVALUATING GATE OXIDE INTEGRITY BY
VOLTAGE RAMP TECHNIQUE
This test method was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the North American Silicon Wafer Committee. Current edition approved for publication by
the North American Regional Standards Committee on December 4, 2003. Initially available at
www.semi.org February 2004; to be published March 2004. Originally published by ASTM International as
ASTM F 1771-97. Last previous edition SEMI MF1392-97 (Reapproved 2002).
1 Purpose
1.1 The technique outlined in this test method is meant
to standardize the procedure, analysis and reporting of
oxide integrity data via the voltage ramp technique
among interested parties. However, since the values
obtained cannot be entirely divorced from the process
of fabricating the test structure, suitable correlations
should be performed based on process needs and
structure selection. This correlation should include
sample size as well as device geometry.
1.2 Measurement of the electrical integrity of oxides
grown on silicon wafers may also be used in-house as a
means of monitoring the quality of furnaces and other
processing steps as well as judging the impact of
changing some processing steps.
1.3 Selection of various edge and area intensive
structures is crucial for isolating the nature of the
defects. Techniques for using such structures to isolate
the nature of detected defects is beyond the scope of
this test method.
1.4 The actual results are somewhat dependent on the
choice of gate electrode. Polysilicon gates have the
advantage of being identical to finished product in
many instances. Even for polysilicon gates, exact
results depend upon values chosen for polysilicon
thickness, doping, and sheet resistance.
2 Scope
2.1 The techniques outlined in this standard are for the
purpose of standardizing the procedure of measure-
ment, analysis, and reporting of oxide integrity data
between interested parties.
2.1.1 This test method makes no representation
regarding actual device failure rates or
acceptance/rejection criteria.
2.1.2 While some suggestions for data analysis are
included in later sections of this test method,
interpretation of results is beyond the scope of this
standard. Any such interpretations should be agreed
upon between interested parties prior to testing. For
example, a variety of failure criteria are included to
permit separation of so-called intrinsic and extrinsic
oxide failures.
NOTE 1: In this regard this test method differs from that
given in SEMI M51, which is focused on application of gate
oxide integrity measurements, as described in this test
method, to determine the density of crystal originated pits in
the wafer under test. SEMI M51 also provides a standardized
procedure for fabricating the MOS capacitors.
2.2 The background of this test method is provided in
Related Information 1.
2.3 This test method covers the procedure for gaging
the electrical strength of silicon dioxide thin films with
thicknesses ranging from approximately 3 nm to 50 nm.
In the analysis of films of 4 nm or less, the impact of
direct tunneling on the current-voltage characteristics,
and hence the specified failure criteria defined in
Section 5.4, must be taken into account. Since oxide
integrity strongly depends on wafer defects,
contamination, cleanliness, as well as processing, the
users of this test method are expected to include wafer
manufacturers and device manufacturers.
2.4 This test method is not structure specific, but notes
regarding options for different structures may be found
in the appendix. The three most likely structures are
simple planar metal-oxide semiconductor (MOS-
capacitors) (fabricated or mercury probe), various
isolation structures (for example, local oxidation of
silicon (LOCOS)), and field effect transistors. This test
method assumes that a low resistance ohmic contact is
made to the backside of each wafer in each case. For a
more detailed discussion of the design and evaluation of
test structures for this test method, the reader is referred
to the EIA/JEDEC Standard 35-1.
2.5 Failure criteria specified in this test method include
both the fixed current limit (soft) and destructive (hard)
types. In the past, use of a fixed current limit of 1 µA or
more virtually ensured measurement of hard failure, as
the thicker, more heavily contaminated oxides of those
days typically failed catastrophically as soon as
measurable currents were passed. The cleaner
processing of thinner oxides now means that oxides will
sustain relatively large currents with little or no
evidence of failure. While use of fixed current limit
testing may still be of value for assessing uniformity
SEMI MF1771-0304 © SEMI 2003, 2004 2
issues, it is widely felt that failure to continue oxide
breakdown testing to the point of catastrophic oxide
failure may mask the presence of defect tails, which are
of critical importance in assessing long-term oxide
reliability. For this reason, this test method makes
provision for use of fixed limit failure criteria if desired
and agreed upon by the parties to the testing, but
specifies that testing be continued until hard failure is
sensed.
2.6 This test method specifically does not include
measurement of a charge-to-breakdown (Q
bd
)
parameter. Industry experience with this parameter
measured in a ramp-to-failure test such as this indicates
that Q
bd
values so obtained may be unreliable
indicators of oxide quality. This is because a large
fraction of the value determined is collected in the last
steps of the test, and the result is subject to large
deviations. Q
bd
should be measured in a constant
current or bounded current ramp test. This test method
is applicable to both n-type and p-type wafers, polished
or having an epitaxial layer. In wafers with epitaxial
layers, the conductivity type of the layer should be the
same as that of the bulk wafer. While not excluding
depletion polarity, it is preferred that measurement
polarity should be in accumulation to void the
complication of a voltage drop across the depletion
layer.
2.7 While this test method is primarily intended for use
in characterizing the SiO
2
-silicon systems as stated
above, it may be applied in general terms to the
measurement of other metal-insulator-semiconductor
structures if appropriate consideration of the
characteristics of the other materials is made.
2.8 Measurement conditions specified in this test
method are conservative, intended for thorough analysis
of high quality oxide-silicon systems, and to provide a
regime in which new users may safely begin testing
without encountering undue experimental artifacts. It is
recognized that some experienced users may be
working in applications where less precise data is
required and a more rapid test is desirable. An example
of this situation is the evaluation of silicon wafer
quality, where a staircase voltage step providing 0.5
MV/cm oxide field strength resolution and a voltage
step duration of 0.2 s has been used. Such test
conditions may be specified when agreed upon as
adequate by all participants to the testing. Because the
dependence of measured parameters upon test
conditions may increase as these conditions depart from
those specified in this test method, it is important that
all parties to these tests use the same set of test
conditions, so that their results are comparable.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the user of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Limitations
3.1 Since this is a dc measurement, care must be taken
to make sure that the wafer has a low resistance ohmic
return contact. This is preferably done with a
metallized contact to the back side of the wafer under
test. In cases where testing must be done on capacitors
in diffused wells of conductivity type opposite to the
substrate, top side contacts carefully designed to
provide uniform, low resistance to all parts of the test
capacitor should be used. A discussion of these design
criteria is given in Standard 35-1.
3.2 It is strongly suggested that testing be done with a
voltage polarity to accumulate the silicon surface
underlying the oxide; positive voltages for n-type
substrates and negative voltages for p-type substrates.
If this is not done, a topside contact to a diffused region
of opposite conductivity type surrounding the capacitor
(a gated diode or transistor) should be used to minimize
the problem of uncontrolled voltage drops across the
inversion layer during testing. This is an absolute
requirement for testing p-type substrate capacitors
under positive bias, where sufficient electrons to
support conduction and breakdown are not available
without the n-type region.
3.3 Evaluation and control of electrical noise in the
current-voltage data taken as part of this test method is
crucial to the proper identification of the failure criteria,
particularly the ln J-V slope change criterion defined in
Section 9.9.4. Approaches for minimizing electrical
noise in the measurements are suggested in Section 7
on Apparatus, and an approach for noise evaluation is
given in Section 10.3.
3.4 Control of the voltage step time may be difficult
when using automated electrometers in a voltage
staircase regime. While the required 100-ms step time
may be set using a delay in the measurement loop, an
additional, uncontrolled delay may be incurred due to
autoranging of the electrometer. The effect is most
pronounced for very low currents, where the measured
value is several orders of magnitude below the
minimum range set by the electrometer software. An
example of this effect is discussed in Section 10.3.
3.5 The method of probing the device may affect the
results. Examples of possible variables are probe
pressure and use of a contact pad versus direct contact
to the gate.
3.6 Use of gate electrode material other than
polysilicon may mask differences in materials and
SEMI MF1771-0304 © SEMI 2003, 2004 3
make the material look worse than it might otherwise
appear if polysilicon gates are used. This is because the
process of forming a gate electrode on an oxide sample
may affect the integrity of that oxide either for better or
for worse. Sputtering or radiation damage
accompanying metal gate deposition may degrade oxide
integrity, while the high temperature annealing and
gettering associated with polysilicon deposition and
doping may improve oxide quality. On the other hand,
stress arising from crystal formation in the polysilicon,
or impurity diffusion along polysilicon grain boundaries
may degrade oxide integrity. Changes of gate-substrate
work function difference may also affect the breakdown
and wearout mechanisms in the oxide. Therefore,
potential effects of gate electrode material choice on
test results must not be neglected.
3.7 The actual values obtained depend somewhat on
the processing involved in fabricating the test structure.
Care must be taken to ensure a consistent processing.
3.8 Wafer temperature during testing should be clearly
defined. While oxide breakdown voltages are not
strongly temperature-dependent, the oxide wearout
mechanism is temperature-sensitive, and large
temperature variations might have an impact on results.
3.9 Warning — Since the voltage and currents
involved are potentially dangerous, appropriate means
of preventing the operator from coming into contact
with the probe tip or other charged surfaces should be
in place before testing.
3.10 When testing very thin oxides, those 10 nm or less
in thickness, special care must be taken to account for
effects arising from the very high specific capacitance
of these films. These may include voltage drops across
the polysilicon gate electrode and the silicon substrate,
and high conduction due to direct tunneling.
3.11 When using a mercury probe for measurements of
this type, care must be taken in the preparation and
control of the oxide surface. Adsorbed organic
contaminant films may affect the electric field
distribution in the oxide. Such films may sometimes be
removed with hot SC-1 cleaning solution; a mixture of
NH
4
OH-H
2
O
2
-H
2
O. Use of a dry nitrogen purge of the
probing ambient is also recommended to minimize
surface contamination effects.
4 Referenced Standards
4.1 SEMI Standard
SEMI M51 — Test Method for Characterizing Silicon
Wafers by Gate Oxide Integrity
4.2 EIA/JEDEC Standards
1
Standard 35 — Procedure for the Wafer-Level Testing
of Thin Dielectrics
Standard 35-1 — General Guidelines for Designing
Test Structures for the Wafer-Level Testing of Thin
Dielectrics
Standard 35-2 — Test Criteria for the Wafer-Level
Testing of Thin Dielectrics
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
5 Terminology
5.1 Definitions
5.1.1 hard failure — destructive failure of an MOS
capacitor associated with rupture of the oxide film.
5.1.1.1 Discussion — This is sensed by an abrupt,
irreversible change in the current-voltage characteristics
of the capacitor. In this test method, hard failure is
determined by a relatively large change in dc
conduction level between voltage steps, or as a change
in the logarithmic slope of the current density-voltage
characteristic.
5.1.2 soft failure — failure of an MOS capacitor sensed
by its passage of an electrical current equal to or greater
than a predetermined value.
5.1.2.1 Discussion — This type of failure may be either
destructive or nondestructive, as in the case of Fowler-
Nordheim or direct tunneling currents.
5.1.3 failure modes A, B, and C — in the reporting of
hard and soft breakdown failure results, data is
sometimes summarized in terms of ranges of oxide field
strength in which the breakdown occurred.
5.1.3.1 Discussion — One set of categories widely
used
2
,
3
is as follows:
• A mode failure: E
ox
< 1 MV/cm
• B mode failure: 1 MV/cm ≤ E
ox
≤ 8 mV/cm
• C mode failure: 8 MV/cm < E
ox
1 Available from Electronic Industries Alliance, 2500 Wilson Blvd.,
Arlington, VA 22201 USA. Tel: 703-907-7500, Fax: 703-907-7501,
Website:
www.eia.org.
2 Yamabe, K., Ozawa, Y., Nadahara, S., and Imai, K., “Thermally
Grown Silicon Dioxide with High Reliability,” in Semiconductor
Silicon 1990, Proceedings Volume 90-7, The Electrochemical
Society, (Pennington, NJ, 1990) pp. 349-363.
3 Yamabe, K., Taniguchi, K., and Matsushita, Y., “Thickness
Dependence of Dielectric Breakdown Failure of Thermal SiO2
Films,” Reliability Physics—21st Annual Proceedings, 1983, p. 184.