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SEMI G5-87 © SEMI 1 980, 199 6 1 SEMI G5-87 STANDARD FOR CERA M IC CHI P CA R RIERS 1 Scope This specification defines the acceptance criteria for co- fired, ceramic ch ip carriers both leaded and lead-less. 2 Applicabl …

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SEMIG4-0302 © SEMI 1982, 2002 12
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SEMI G5-87 © SEMI 1980, 19961
SEMI G5-87
STANDARD FOR CERAMIC CHIP CARRIERS
1 Scope
This specification defines the acceptance criteria for co-
fired, ceramic chip carriers both leaded and lead-less.
2 Applicable Documents
2.1 ANSI Specification
1
S Y 14.5 — Dimensioning and Tolerancing
2.2 Federal Specification
2
QQ-N-290 — Nickel Plating
2.3 JEDEC Specification
3
Pub. No. 95 — Registered and Standard Outline for
Solid State Products
2.4 Military Specifications
4
MIL-STD-105 — Sampling Procedures and Tables for
Inspection by Attributes
MIL-STD-883 — Test Methods and Procedures for
Microelectronics
MIL-STD-7883 — Brazing
MIL-M-38510 — General Specification for
Microcircuits
MIL-STD-45204 — Gold Plating, Electrodeposited
2.5 SEMI Specifications
SEMI G8 — Test Method for Gold Plating Quality
SEMI G25 — Test Method for Measuring the
Resistance of Package Leads
SEMI G6 — Test Method for Seal Ring Flatness
3 Selected Definitions
braze — An alloy with a melting point equal to or
greater than 600°C.
castellation — That series of ribs and metallized
indentations that define edge contact regions (see
Figure 1).
1 ANSI, 1430 Broadway, New York, NY 10018
2 Military Standards, Naval Publications and Form Center, 5801
Tabor Ave., Philadelphia, PA 19120
3 JEDEC, 2001 Eye Street, N.W., Washington, D.C. 20006
4 General Services Administrator, 4th and D Streets, SW, Room
6039, Washington, D.C. 20407
fired — A process or technology to manufacture
products in which the ceramic and refractory
metallization are fired simultaneously.
contact pad — That metallized pattern that provides
mechanical or electrical connection to the external
circuitry.
die attach surface — See Figure 3.
footprint — Contact pad pattern.
layer — A dielectric sheet with or without metallization
that performs a discrete function as a part of the
package.
lead offset — Alignment of leads across the package.
pullback — The linear distance between the edge of the
ceramic and the first measurable metallization and/or
glass interface (see Figures 4 and 5).
rundown — See Figures 4 and 5.
seal-area — A dimensional outline area designated for
either metallization or bare ceramic to provide a surface
area for sealing (see Figure 3).
terminal — Case outline at point of entry or exit of an
electrical contact.
TIR — Total Indicator Reading.
4 Ordering Information
Purchase order for ceramic chip carriers furnished to
this specification shall include the following items:
1. Quantity
2. Drawing — The drawing(s) for ceramic chip
carriers shall specify the following information:
a. Drawing number and revision level.
b. Number of terminals and terminal center line
spacing.
c. Lead material and dimensions.
d. Critical material properties.
e. Type and thickness of plating.
f. Package dimensions per ANSI Y14.5.
g. Internal bonding patterns.
h. Minimum exposed metallized bond finger length
and width.
SEMI G5-87 © SEMI 1980, 1996 2
i. Portion of external footprints connected to die
attach area and/or seal ring.
j. Terminal #1 position, internal and external.
k. Certification (optional).
l. Method of test and measurements.
m. Electrical, mechanical, environmental
requirements.
3. Reference to this specification
4. Any exception to print or specification
5 Dimensions and Permissi ble Variations
5.1 The dimensions of ceramic chip carriers shall
conform to those specified in the customer drawing,
and be within the outline of JEDEC Publication No. 95.
NOTE: A dimensioning scheme and measurement fixture are
under task force review.
5.2 Critical Material Parameters
5.2.1 Ceramic
5.2.1.1 Alumina, content 90% minimum.
5.2.1.2 Color — Dark or white.
5.2.2 Metallization
5.2.2.1 Refractory metallization.
5.2.2.2 Plating (if designated) per MIL-M-38510.
5.2.2.3 Nickel per QQ-N-290
5.2.2.4 Gold per MIL-STD-45204, Type III.
5.2.2.5 Gold Plating Quality see SEMI G8.
5.2.3 Braze per MIL-STD-7883.
5.2.4 Lead per MIL-STD-23011.
5.2.4.1 Iron Nickel Cobalt alloy per MIL-M-38510,
Type A.
5.2.4.2 Iron Nickel alloy per MIL-M-38510, Type B.
6 Functional Testing
The following tests are recommended for functional
evaluation of ceramic chip carriers. (The conditions of
acceptance to be negotiated between the customer and
the vendor.)
6.1 Die Attach
6.2 Pre-Seal Die Shear — (See Section 10.1.6.)
6.3 Wire Bond
6.4 Pre-Seal Bond Pull — (See Section 10.1.7.)
6.5 Seal
6.6 Environmental Test — (See Sections 10.1.1
through 10.1.13.)
6.7 Hermeticity — (See Section 10.1.14) Lid Torque
or Shear (for glass seal parts).
6.8 Post-Seal Bond Pull — (See Section 10.1.7.)
6.9 Post-Seal Die Shear — (See Section 10.1.6.)
7 Incoming Testing
7.1 Visual — (See Section 8.)
7.2 Dimensions
7.3 Functional — (See Section 6.)
7.4 Standard Tests
7.4.1 Electrical — (See SEMI G25.)
7.4.2 Gold Plating Quality — (See SEMI G8.)
7.4.3 Trim
7.4.4 Lead Integrity —(See Section 10.1.15.)
7.4.5 Solderability — (See Section 10.1.16.)
8 Visual
8.1 Applicable Definitions
blister (bubble) ceramic — Any separation within the
ceramic which does not expose underlying ceramic
material.
blister (bubble) metal — Any localized separation
within the metallization or between the metallization
and ceramic which does not expose underlying metal or
ceramic material.
burr — An adherent fragment of excess parent material
at the component edge.
chip — A region of ceramic missing from the surface or
edge of a package which does not go completely
through the package. Chip size is given by its length,
width, and depth from a projection of the design plan-
form (see Figure 2).
crack — A cleavage or fracture, internal or external.
die attach surface — See Figure 3.
discoloration — Any non-uniform color change of the
package plating.
foreign material — An adherent particle other than
parent material of that component.
LSI — Large scale integration.