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SEMI M2-1103 © SEMI 1985, 2003 3 NOTE 4: Care should be taken in converting between carrier density and resistivity using SEMI MF723. Multiple conversions may introduce differences in values . For example, converting fro…
SEMI M2-1103 © SEMI 1985, 2003 2
3.2 Other Standards
1
ANSI/ASQC Z1.4 — Sampling Procedures and Tables
for Inspection by Attributes
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
4 Terminology
4.1 Many terms relating to silicon technology are
defined in SEMI MF1241.
4.2 Descriptions of other epitaxial wafer defects
covered in Table 1 are given in SEMI MF154.
4.3 Other terms are defined as follows:
4.3.1 autodoping, of an epitaxial layer —
incorporation of dopant originating from the substrate
into the epitaxial layer. Also called self-doping.
NOTE 1: Sources of autodoping can be the back and front
surfaces and edges of the substrate, other substrates in the
reactor, the susceptor, or other parts of the deposition
assembly.
4.3.2 chemical vapor deposition, in semiconductor
technology — a process in which a controlled chemical
reaction produces a thin surface film.
NOTE 2: Epitaxial growth is an example of a special case of
chemical vapor deposition (CVD).
4.3.3 edge crown — the difference between the surface
elevation 1/8 inch (3.2 mm) from the edge of the wafer
and the elevation at the wafer edge.
4.3.4 effective layer thickness, of an epitaxial layer —
the depth from the front surface in which the net carrier
density is within the specified limits.
4.3.5 epi profile slope, of an epitaxial layer — the
difference between the net carrier density at 0.75 of the
layer thickness and the net carrier density at 0.25 of the
layer thickness divided by one-half the layer thickness:
t
NN
tt
5.0
slope profile epi
25.075.0
−
= (1)
where:
N = net carrier density, cm
−3
, and
t = layer thickness, µm.
4.3.6 epitaxial layer — a layer of single crystal
semiconductor material grown on a host substrate that
determines its orientation.
1 American Society for Quality Control, 611 East Wisconsin Avenue,
Milwaukee, WI 53202
4.3.7 epitaxy — The growth of a single crystal layer on
a substrate of the same material, homoepitaxy; or on a
substrate of different material with a compatible crystal
structure, heteroepitaxy.
4.3.8 flat zone, of an epitaxial layer — The depth from
the front surface to the point where the net carrier
density is 20% greater than or less than the average net
carrier density (see Section 8.3.2) of the region between
0.25 and 0.75 of the layer thickness.
4.3.9 thickness, of an epitaxial layer — The distance
from the surface of the wafer to the layer-substrate
interface.
4.3.10 transition width, of an epitaxial layer deposited
on a more heavily doped substrate of the same
conductivity type — The difference between the layer
thickness as determined by infrared reflectance (see
Section 8.3.1) and the flat zone based on the same
thickness measurement.
5 Ordering Information
5.1 Purchase orders for the epitaxial layer on substrates
furnished to this specification shall include the
following items:
5.1.1 Substrate characteristics,
5.1.2 Silicon source (if required) (see Note 3),
5.1.3 Conductivity type and doping source (see Note
3),
5.1.4 Etch removal (if required),
5.1.5 Center-point thickness and thickness tolerances,
5.1.6 Radial thickness variation range,
5.1.7 Center-point net carrier density and net carrier
density tolerances (or resistivity and resistivity
tolerances) (see Note 4),
5.1.8 Radial net carrier density (or resistivity) variation
range (see Note 4),
5.1.9 Epitaxial wafer defect limits,
5.1.10 Methods of test and measurements (see Section
8),
5.1.11 Lot acceptance procedures (see Section 7),
5.1.12 Certification (if required) (see Section 9), and
5.1.13 Packing and marking (see Section 10).
NOTE 3: The dopant, doping method, and growth method are
difficult to ascertain in the finished wafers. Verification test
procedures or certification of these characteristics shall be
agreed upon between the supplier and the purchaser (see
Section 9).
SEMI M2-1103 © SEMI 1985, 2003 3
NOTE 4: Care should be taken in converting between carrier
density and resistivity using SEMI MF723. Multiple
conversions may introduce differences in values. For
example, converting from carrier density (C
i
) to resistivity
and back to carrier density (C
f
), may result in C
i
not equaling
C
f
.
6 Requirements
6.1 The substrate shall conform to SEMI M1 and to the
appropriate polished silicon wafer standard.
6.2 Epitaxial wafer defects shall not exceed the limits
as given in Table 1.
NOTE 5: When an unetched wafer is observed for slip, it is
impossible to differentiate between slip and linear misfit lines.
6.3 Layer Thickness Variation — Unless otherwise
specified, the radial thickness variation shall be
determined from values measured at the center and half
radius (R/2) locations, on diameters both parallel and
perpendicular to the primary flat, and shall be ≤ 6%
defined as follows:
100
2
(%)Variation
max
×
−
=
C
C
R
(2)
where R/2 denotes one of the layer thickness values
measured at half radius and C denotes the value at the
center point.
6.4 Net Carrier Density Variation — The radial net
carrier density variation shall be determined from
values measured at the center and half radius (R/2)
locations, on diameters both parallel and perpendicular
to the primary flat, and shall be ≤10% for net carrier
density ≥1 × 10
15
cm
-3
and ≤15% for net carrier density
<1 × 10
15
cm
-3
defined as follows:
100
2
(%)Variation
max
×
−
=
C
C
R
(3)
where R/2 denotes one of the net carrier density values
measured at half radius and C denotes the value at the
center point.
7 Sampling
7.1 Unless otherwise specified, appropriate sample
sizes shall be selected from each lot according to
ANSI/ASQC Z1.4. Each quality characteristic shall be
assigned an acceptable quality level (AQL) in
accordance with ANSI/ASQC Z1.4. Inspection levels
shall be agreed upon between supplier and purchaser.
7.2 Unless otherwise specified, the following AQL’s
shall be assigned:
7.2.1 Epitaxial layer thickness, 6.5%,
7.2.2 Epitaxial layer net carrier density, 6.5%,
7.2.3 Epitaxial wafer defects, cumulative, 4.0%.
8 Test Methods
8.1 Measurements shall be carried out in conformance
with the specified SEMI methods. Where no methods
are specified or where choices are given, the supplier
and purchaser shall agree in advance on the means for
making the measurement.
8.2 Substrate — Determine in accordance with
methods defined in SEMI M1.
8.3 Epitaxial Layer
8.3.1 Thickness — Determine in accordance with
SEMI MF95 or SEMI MF110.
NOTE 6: There is a possibility that various types of infrared
reflectance instrumentation may result in different values of
epitaxial layer thickness. Therefore, the instrumentation used
shall be agreed upon between supplier and purchaser.
8.3.2 Net Carrier Density — Determine by method(s)
agreed upon between supplier and purchaser.
NOTE 7: SEMI MF1392 and SEMI MF1393 are methods
for measuring net carrier density using a mercury probe
contact. If resistivity is measured, as by SEMI MF374 or
SEMI MF525, conversion to dopant density shall be made
using SEMI MF723. Net carrier density of very heavily doped
layers (or substrates) may be found using SEMI MF398. Net
carrier density profiles may be determined directly in
accordance with SEMI MF1392 or SEMI MF1393 or
indirectly in accordance with SEMI MF672, with conversion
from resistivity to net carrier density in accordance with
SEMI MF723. If the method used for determining the net
carrier density profile is not the same as that used to
determine the center point net carrier density, correlation
between the two methods used shall be established.
8.3.3 Epitaxial Wafer Defects — Determine in
accordance with the methods given in Table 1.
8.3.3.1 Surface inspection shall be performed before
any other testing. Wafers may be cleaned prior to
inspection to minimize difficulty in the visual
inspection of defects other than foreign matter.
8.3.3.2 Inspection for slip shall be done using grid
elements constructed in accordance with SEMI M17.
An element is defective if it contains one or more slip
lines. The total number of defective elements shall be
less than or equal to n, where n is listed in Table 1.
8.4 If substrates of different type and net carrier
density than the product substrates are to be used for
deposition control, their type, net carrier density, and
quantity per run or lot shall be agreed upon between
supplier and purchaser.
SEMI M2-1103 © SEMI 1985, 2003 4
9 Certification
9.1 Upon request of the purchaser in the contract or
order, a manufacturer’s or supplier’s certification that
the material was manufactured and tested in accordance
with this specification, together with a report of the test
results, shall be furnished at the time of shipment.
9.2 The user and supplier may agree that the material
shall be certified as “capable of meeting” certain
requirements. In this context, “capable of meeting”
shall signify that the supplier is not required to perform
the appropriate tests in Section 8; however, if the user
performs the test and the material fails to meet the
requirement, the material may be subject to rejection.
10 Packing and Package Labeling
10.1 Special packing requirements shall be subject to
agreement between the supplier and the purchaser.
Otherwise, all wafers shall be handled, inspected, and
packed in such a manner as to avoid chipping,
scratches, and contamination, and in accordance with
the best industry practices to provide protection against
damage during shipment.
10.2 The wafers supplied under these specifications
shall be identified by appropriately labeling the outside
of each box or container, and each subdivision thereof,
in which it may reasonably be expected that the wafers
will be stored prior to further processing. Identification
shall include supplier’s name and reference number,
purchaser’s P.O. number, quantity, dopant, orientation,
conductivity type of substrates and epitaxial layers,
carrier density (or resistivity, if so specified in the
purchase order or contract), and thickness of the
epitaxial layer. The reference number assigned by the
supplier shall provide ready access to information
concerning the fabrication history of the particular
wafers in that lot. Such information shall be retained on
file at the manufacturer’s facility for at least one year
after the particular lot has been shipped.