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SEMI G33-90 © SEMI 198 6, 1996 3 2. 63/37 — 63% Sn /37% Pb 3. 10/88/2 — 10% Sn /88% Pb/2% A g 6.2.4 Pi n Material — C D A150, OF H C Co pper, Zircon i um alloy per ASTM B 1 52. 6.3 Thick Film Dielectr ic — An am o r p ho…

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SEMI G33-90 © SEMI 1986, 1996 2
combination of metals is applied to a suitable substrate
and fired.
rundown — The vertical extension of metallization
from the ceramic (see Figure 2).
seal area — A dimensional outline area designated to
provide a surface for sealing.
seating plane — Defined by the standoff features or the
package base plane if no standoff is used (see Figure 3).
SLAM — Abbreviation for “Single Layer Alumina
Metallization,” which denotes a package design without
a physical die attach cavity.
solder — An alloy with a melting point equal to or less
than 427°C.
standoff — The designed separation between the base
plane and the seating plane created by a physical
feature. Standoff use, configuration, and placement is
optional (see Figure 3).
terminal — Case outline at point of entry or exit of an
electrical contact.
thick film metallization — The process by which a thin
layer of metal (usually in the 0.3 to 1.0 µm range) is
applied to a suitable substrate by methods including
sputtering, vacuum evaporation and chemical vapor
deposition.
TIR — Total Indicator Reading.
window frame — A separate member of ceramic which
is joined to the surface of the package on which a flat
lid is attached for sealing.
4 Ordering Information
Purchase orders for pin grid array packages furnished to
this specification shall include the following items:
1. Drawing number and revision level
2. Certification requirements
3. Quantity
4. Reference to this document
5. Any exceptions to print or specifications
5 Dimensions and Permissi ble Variations
The dimensions of the pin grid array package shall
conform to SEMI Standards or to the customer
drawing, and be within the outline of the appropriate
JEDEC standard.
6 Material Parameters
The definitions, defects, and functional testing
described in this specification relate directly to a
nominal package made with the following materials.
They may also be applicable to similar pin grid array
packages made with other materials.
6.1 Ceramic Properties
6.1.1 Materials — Alumina content 90% minimum.
Beryllia content to be in excess of 98.5% BeO.
6.1.2 Color — Dark or white.
6.2 Metal Properties
6.2.1 Plating
6.2.1.1 Plating finish shall be per MIL-M-38510;
Nickel Plating (if designated) shall be per QQ-N-290A,
50 µ"–350 µ" (0.1300 mm–0.08890 mm). Gold plating
(if desired) shall conform to MIL-G-45204, Type III
and 50 µ"–225 µ" (0.1300 mm–0.05080 mm).
6.2.2 Metallization
6.2.2.1 Metallized circuits and areas can be thick film,
thin film or refractory post-metallized. Such
metallization materials may be, but are not limited to,
the following:
1. Thick Film Materials
a. Gold (Au) and Gold Alloys
b. Silver (Ag)
c. Silver - Platinum - Palladium (AgPtPd)
d. Silver - Palladium - Platinum (AgPdPt)
e. Copper (Cu)
2. Thin Film Materials
a. Copper (Cu)
b. Chromium (Cr)
c. Nickel (Ni)
d. Titanium (Ti)
4. Refractory Materials
a. Molybdenum - Manganese (MoMn)
b. Molybdenum - Tungsten (MoW)
6.2.3 Solder — Solder compositions used in the
manufacture of pressed ceramic pin grid array packages
shall include, but not be limited to, the following, per
QQ-S-571E:
1. 10/90 — 10% Sn/90% Pb
SEMI G33-90 © SEMI 1986, 19963
2. 63/37 — 63% Sn/37% Pb
3. 10/88/2 — 10% Sn/88% Pb/2% Ag
6.2.4 Pin Material — CDA150, OFHC Copper,
Zirconium alloy per ASTM B 152.
6.3 Thick Film Dielectric — An amorphous or
polycrystalline glass or approved equivalent ranging in
thickness from 0.013 mm (0.0005") to 0.038 mm
(0.0015").
7 Defect Limits
A magnification of 10× shall be used to inspect the
packages unless otherwise specified.
7.1 Ceramic
7.1.1 Cracks — Per MIL-STD-883, Method 2009.
7.1.2 Chips — (See Figure 1.)
7.1.2.1 General
7.1.2.1.1 Corner — Chips shall not exceed 0.762 mm
(0.030") length × 0.762 mm (0.030") width × 0.762 mm
(0.030") depth (see Figure 1-B).
7.1.2.1.2 Edge — Chips shall not exceed 1.52 mm
(0.060") length × 0.635 mm (0.025") width × 0.635 mm
(0.025") depth (see Figure 1-A).
7.1.2.1.3 Chips cannot encroach upon contact pad or
penetrate metallization.
7.1.2.2 Seal Area
7.1.2.2.1 Design With Window Frame — Chips shall
not exceed 0.635 mm (0.025") length × 0.635 mm
(0.025") width × 0.635 mm (0.025") depth maximum.
Chips cannot reduce the seal area width by more than
1/3 of the design width.
7.1.2.2.2 Design Without Window Frame — See
Section 7.5 of this specification for dielectric inspection
criteria.
7.1.2.3 Cavity Edges
7.1.2.3.1 Chips in the edges around the cavity shall not
exceed 0.381 mm (0.015") along the edges or 0.127
mm (0.005") in depth.
7.2 Package Flatness — 0.004 inch/inch maximum
7.2.1 Seal Area Flatness
7.2.1.1 With Window Frame
Seal Area Size Seal Area Flatness (TIR)
0–12.7 mm (0.000"-0.500") 0.051 mm (0.002") MAX
12.72–19.05 mm (0.501"-0.750") 0.076 mm (0.003") MAX
19.07 mm & greater (0.751") 0.101 mm (0.004") MAX
7.2.1.2 Without Window Frame — Flatness shall be
0.004" per inch maximum TIR.
7.2.2 Die Attach Area Flatness
Die Attach Area Size
Die Attach Area Flatness
(TIR)
0–12.7 mm (0.000"-0.500") 0.051 mm (0.002") MAX
12.72–19.05 mm (0.501"-0.750") 0.088 mm (0.0035") MAX
7.3 Metallization Misalignment (see Figure 2)
7.3.1 Metallization Rundown — For the internal cavity
shall not exceed 25% of the cavity depth, with a
minimum of 0.127 mm (0.005") minimum isolation
required.
7.3.2 Wire Bond Finger Pullback — 0.254 mm
(0.010") maximum.
7.3.3 Wire Bond Finger Rundown — Not to exceed
1/3 of the ceramic cavity depth; 0.127 mm (0.005")
isolation required.
7.3.4 Pattern Isolation — Dimension shall not be
reduced by more than 50% of the design.
7.4 Metallization Voids
7.4.1 Wire Bond Finger — Must be free of voids or
bare spots in the bonding area as defined by customer
drawing.
7.4.2 Die Attach Surface
7.4.2.1 SLAM Design — Three voids are allowed, with
a maximum of 0.127 mm (0.005") diameter separated
by a distance greater than 0.254 mm (0.010"). Voids
within 0.254 mm (0.010") of perimeter of die attach
print area shall not be considered as the basis for
rejection.
7.4.2.2 Cavity Design — Three voids are allowed with
a maximum of 0.254 mm (0.010") diameter separated
by a distance greater than 0.254 mm (0.010"). Voids
within 0.381 mm (0.015") of die attach cavity wall shall
not be considered as the basis for rejection.
7.4.3 Solder
7.4.3.1 Pin Coating — Solder wetting acceptability
shall be per criteria in MIL-STD-883, Method 2003.
SEMI G33-90 © SEMI 1986, 1996 4
7.4.3.2 Contact Pad Coating — A minimum of 50%
filleting must exist on the pin to pad solder joint with
no exposed copper. A maximum of 0.889 mm (0.035")
height of solder shall be allowed on pin to pad solder
joints.
7.5 Dielectric
7.5.1 Voids — No single void in the dielectric shall
expose two adjacent traces. Voids in the dielectric
closer than 0.635 mm (0.025") shall not expose two
adjacent traces.
7.5.2 Contamination — There shall be no
contamination or foreign material upon dielectric with a
diameter greater than 0.381 mm (0.015").
8 Sampling
Sampling size must meet the requirements of MIL-
STD-105 or MIL-M-38510 or as agreed to between
vendor and customer. Single, double, or multiple
samples may be used per vendor and customer
agreement.
9 Test Methods
9.1 Mechanical, electrical, and thermal test methods
are per MIL-STD-883, unless otherwise noted.
9.1.1 Lead Pull — Under the test condition of five (5)
pounds ± one quarter (1/4) pound, pull at an angle of
20° or less from the pins vertical line measured
perpendicular to the package, there shall be no visible
separation of the solder joint under 10× magnification.
9.1.2 Lead Fatigue — Shall be per MIL-STD-883,
Method 2004, Test Condition B2, Paragraph 3.2.
9.2 Functional Test Methods
9.2.1 Die Attach Quality — Destructive die shear test
shall be after environmental testing shall be per MIL-
STD-883, Method 2019, Paragraph 3.2C.
9.2.2 Wire Bond Quality — Minimum pre-seal and
post-seal bond strength test is per MIL-STD-883,
Method 2011, Test Condition D. Reject for bonds
which cause metallization to lift from the package or
fail to meet minimum strength requirement.
9.2.3 Solderability — Per MIL-STD-883, Method
2003.
9.2.4 Insulation Resistance Test — Per MIL-STD-883,
Method 1003, Condition D.
9.2.5 Hermetic and Environmental Testing — Per
MIL-STD-883.
9.2.5.1 The hermetic integrity of the package must be
maintained after all environmental testing. Hermetic
checks shall comply with MIL-STD-883, Method 1014
Test Conditions A, B, C or D.
9.2.5.2 Environmental testing shall include, but not be
limited to, the following:
1. Temperature Cycle per MIL-STD-883, Method
1010, Condition B.
2. Thermal Shock per MIL-STD-883, Method 1011,
Condition B.
3. Centrifuge per MIL-STD-883, Method 2001,
Condition E. Y1 axis only — cavity up; Y2 axis
only — cavity down. (optional)
4. Mechanical Shock per MIL-STD-883, Method
2002, Condition B.
5. Vibration per MIL-STD-883, Method 2007,
Condition A.
NOTE: Package applications requiring a heat sink attach will
have the environmental tests (temperature cycle, shock, etc.)
evaluated on an individual basis. The material, form factor
and method of attachment used for heat sinks may result in
severe stresses on the package assembly during environmental
testing. Actual accelerated test requirements should be based
on the expected product application environment and may be
less stringent than those tests for packages without heat sinks.
10 Sequence of Events and I ncoming Testing
During incoming inspection, the sequence of testing
shall be:
1. Visual
2. Dimensional
3. Functional
a. Die Attach
b. Wire Bond
c. Pre-Seal Wire Pull
d. Seal
e. Heat Sink Attach (if applicable)
f. Environmental Test
g. Fine Leak, MIL-STD-883, Method 1014,
Condition B
h. Gross Leak, MIL-STD-883, Method 1014,
Condition C
i. Post-Seal Bond Pull
j. Radiography
k. Die Shear, MIL-STD-883, Method 2019
l. Solderability, MIL-STD-883, Method 2003