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SEMI M3-0304 © SEMI 1978, 2004 10 RELATED INFORMATION 2 RECOMMENDED SURFACE FINI SH CHARACTERISTICS FOR SAPPHIRE SUBSTRATES NOTICE: This related information is not an official part of SEMI M3 and was derived fr om the or…

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SEMI M3-0304 © SEMI 1978, 2004 9
Table R1-1 Recommended Sapphire Substrate Defect Limits
Item Characteristics Max Defect Limit AQL (see NOTE 6) Illumination Notes
1 SCRATCHES
Maximum Number
Maximum Length
3
R/2
High Intensity 1
2 PITS
Maximum Number
2" Diameter Substrate
3" Diameter Substrate
100 mm Diameter Substrate
125 mm Diameter Substrate
150 mm Diameter Substrate
4
9
15
20
25
4% Cum. 1, 2
3 HAZE None — see NOTE 4 4% Cum. 4
4 CONTAMINATION/PARTICULATE
Maximum Number
2" Diameter Substrate
3" Diameter Substrate
100 mm Diameter Substrate
125 mm Diameter Substrate
150 mm Diameter Substrate
4
9
15
20
25
4% Cum. Diffuse 1, 2
5 CONTAMINATION/AREA None
6 EDGE CHIPS
Maximum Number
Maximum Radial Penetration
Maximum Single Chip
Peripheral Length
Maximum Cumulative
Peripheral Length
see NOTE 3
2
0.12" (3 mm)
0.250" (6.35 mm)
0.250" (6.35 mm)
4% Cum. Diffuse 3
7 CRACKS, CROW' S FEET see NOTE 6 6
8 CRATERS None 1, 5
9 DIMPLES None 1
10 GROOVES None 4% Cum. 1, 5
11 MOUNDS None 1, 5
12 ORANGE PEEL None Diffuse 1
13 SAW MARKS None 1, 5
14 STRIATIONS
SLICE BACK SURFACE
15 CHIPS see NOTE 3 see NOTE 3 Diffuse 3
16 CRACKS, CROW' S FEET None see Note 6 6
17 CONTAMINATION/AREA None
18 SAW MARKS
Incidence
Maximum Depth
N.A. see Note 5 5
NOTE 1: The outer 4 mm annulus is excluded from these criteria.
NOTE 2: Ninety percent of substrate shall be free of contaminants after pre-inspection treatment. Balance of substrate may have light-reflecting
particles up to the limit established for Item 2 — Pits.
NOTE 3: All chips shall be beveled. Chips less than 0.4 mm should not be counted.
NOTE 4: Haze refers to epitaxial silicon appearance only, not to condition of polished sapphire substrate.
NOTE 5: These defects are not observed in SOS wafers. Terms remain for convenient reference to silicon specification.
NOTE 6: Cracks are observed in sapphire substrates as fractures or as surface separations along cleavage planes. The cumulative AQL for both
front surface and back surface of substrate is 4% for both. Crow’s feet see Note 5.
SEMI M3-0304 © SEMI 1978, 2004 10
RELATED INFORMATION 2
RECOMMENDED SURFACE FINISH CHARACTERISTICS FOR
SAPPHIRE SUBSTRATES
NOTICE: This related information is not an official part of SEMI M3 and was derived from the original edition of
the specifications which erroneously included this optional material as a part of the text of the specification. This
related information was approved for publication by full letter ballot procedure on September 3, 2003.
R2-1 Front Surface Finish
R2-1.1 The substrate should be polished on one side suitable for the epitaxial growth of silicon.
R2-1.2 The quality of this surface may be determined by optical examination at 70× using Nomarski interference
contrast microscopy after etching the substrate in potassium hydroxide at 310°C for one to three minutes.
R2-1.3 The photomicrographs in Figures R2-1 through R2-4 may be used as a surface quality guide.
R2-1.3.1 Figure R2-1 shows an acceptable surface.
R2-1.3.2 Figures R2-2 and R2-3 show questionable surfaces that are subject to individual evaluation.
R2-1.3.3 Figure R2-4 shows an unacceptable surface.
R2-2 Back Surface Finish
R2-2.1 The recommended back surface finish is approximately 32 µin, rms, as determined by stylus or optical
profilometer.
Figure R2-1
Acceptable
Surface
Figure R2-3
Questionable
Surface
Figure R2-2
Questionable
Surface
Figure R2-4
Unacceptable
Surface
Figures R2-1 through R2-4
Illustrations of Acceptable, Unacceptable, and Questionable Sapphire Substrate Front Surface Finishes.
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant
literature respecting any materials mentioned herein. These standards are subject to change without notice.
The user’s attention is called to the possibility that compliance with this standard may require use of copyrighted
material or of an invention covered by patent rights. By publication of this standard, SEMI takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M4-1103 © SEMI 1978, 2003 1
SEMI M4-1103
SPECIFICATIONS FOR SOS EPITAXIAL WAFERS
This specification was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the North American Silicon Wafer Committee. Current edition approved by the North
American Regional Standards Committee on July 27, 2003. Initially available on www.semi.org October
2003; to be published November 2003. Originally published in 1978; previously published July 2003.
1 Purpose
1.1 These specifications cover requirements for
monocrystalline silicon epitaxial layers on sapphire
substrates, used for semiconductor device manufacture.
The combination of a silicon epitaxial layer on a
sapphire substrate is known as a silicon on sapphire
(SOS) epitaxial wafer. By outlining an inspection
process and defining various reject criteria, both
suppliers and purchasers can uniformly define epitaxial
layer quality.
1.2 The defects discussed originate from two sources:
those which are caused by imperfection in the sapphire
substrate and those related to the epitaxial layer,
including handling and packaging.
2 Scope
2.1 The primary standardized properties set forth in
this specification relate to physical, dimensional, and
electrical characteristics of SOS epitaxial wafers.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Referenced Standards
3.1 SEMI Standard
SEMI M3 — Specifications for Polished
Monocrystalline Sapphire Substrates
SEMI MF81 — Test Method for Measuring Radial
Resistivity Variation on Silicon Wafers
SEMI MF95 — Test Method for Thickness of Epitaxial
Layers of Silicon on Substrates of the Same Type by
Infrared Reflectance
NOTE 1: Modifications to this procedure are required for use
on SOS wafers.
SEMI MF110 — Test Method for Thickness of
Epitaxial or Diffused Layers in Silicon by the Angle
Lapping and Staining Technique
SEMI MF154 — Guide for Identification of Structures
and Contaminants Seen on Specular Silicon Surfaces
SEMI MF374 — Test Method for Sheet Resistance of
Silicon Epitaxial, Diffused, Polysilicon, and Ion-
implanted Layers Using an In-Line Four-Point Probe
with the Single-Configuration Procedure
SEMI MF523 — Practice for Unaided Visual
Inspection of Polished Silicon Wafers
SEMI MF673 — Test Methods for Measuring
Resistivity of Semiconductor Slices or Sheet Resistance
of Semiconductor Films with a Noncontact Eddy-
Current Gage
3.2 ASTM Standards
1
E 122 — Practice for Choice of Sample Size to
Estimate the Average Quality of a Lot or Process
3.3 Other Standard
2
ANSI/ASQC Z1.4-1993 — Sampling Procedures and
Tables for Inspection by Attributes
NOTICE: Unless otherwise indicated, all documents
cited shall the the latest published versions.
4 Terminology
4.1 Definitions
4.1.1 deposition — the technique involved in the vapor
deposition of single-crystal silicon on oriented sapphire
substrates.
4.1.2 dopant — a chemical element, usually from the
third or fifth columns of the periodic table (typically
phosphorous, arsenic, or boron), incorporated in trace
amounts in the epitaxial layer to establish its
conductivity type and resistivity.
4.1.3 doping — the process of incorporation of a
dopant into the epitaxial layer while the film is
growing.
4.1.4 epitaxial layer — the layer of semiconductor
material that is grown on the substrate.
1 ASTM International, 100 Barr Harbor Drive, West Conshohoken,
PA 19428-2959, USA, Website: www.astm.org, (PracticeE 122 may
be found in Volume 14.02 of the Annual Book of ASTM Standards.)
2 American National Standards Institute, Headquarters: 1819 L
Street, NW, Washington, DC 20036, USA. Telephone: 202.293.8020;
Fax: 202.293.9287, New York Office: 11 West 42nd Street, New
York, NY 10036, USA. Telephone: 212.642.4900; Fax:
212.398.0023, Website: www.ansi.org