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SEMI G38-0996 © SEMI 1987, 2004 9 Units: °C/W Air Velocity (m/s) Sample No. 0 1 3 5 1 2 3 4 5 6 7 8 9 10 Average NOTICE: SEMI makes no warranties or represen tations as to the suitability o f the standards set forth here…
SEMI G38-0996 © SEMI 1987, 2004 8
APPENDIX 1
REPORT FORMAT
NOTICE: This appendix was approved as an official part of SEMI G38 by full letter ballot procedure.
The following format is a sample of report format:
1. Description of Package
1.1 Package Type
Package Name ________________ (per JEDEC or EIAJ)
Pin Counts ________________ pins
Special Specification ________________ Yes ________________ No
1.2 Test Chip
Chip per SEMI G32 ________________ Yes ________________ No
Chip Size ________________ mm x ________________ mm
Chip Thickness ________________ mm
1.3 Leadframe
Leadframe Material Fe/Ni Alloy, Cu, Cu Alloy, Other (________________)
Leadframe Thickness ________________ mm
Die Pad Size ________________ mm x ________________ mm
1.4 Package Dimension & Compound
Package Size ________________ mm x ________________ mm
Package Thickness ________________ mm
Compound Material ________________________________
1.5 Others
Die Attach Material ________________________________
Heat Sink/Spreader ________________ Yes ________________ No
2. Description of Test Board
Test Board per SEMI G42 ________________ Yes ________________ No
No. of Layers ________________________________
3. Measurement Result
Power Dissipation ________________ W
SEMI G38-0996 © SEMI 1987, 2004 9
Units: °C/W
Air Velocity (m/s)
Sample No.
0 1 3 5
1
2
3
4
5
6
7
8
9
10
Average
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant
literature respecting any materials mentioned herein. These standards are subject to change without notice.
The user’s attention is called to the possibility that compliance with this standard may require use of copyrighted
material or of an invention covered by patent rights. By publication of this standard, SEMI takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI G39-89 © SEMI 1986, 19891
SEMI G39-89
SPECIFICATION FOR BRAZED LEAD FLATPACK CONSTRUCTIONS,
INCLUDING LEADFRAMES, SUITABLE FOR AUTOMATED ASSEMBLY
1 Preface
This specification defines the standard requirements for
co-fired ceramic brazed lead flatpack package
constructions intended for automated assembly to
printed wiring boards. Acceptance criteria for package
constructions, including leadframes, are included.
2 Applicable Documents
2.1 ANSI Standard
1
ANSI Y14.5 — Dimensioning and Tolerancing
2.2 Federal Specification
2
QQ-N-290 — Nickel Plating
2.3 JEDEC Standard
3
JEDEC Pub 95 — Registered and Standard Outlines for
Solid State Products
2.4 Military Specifications
2
MIL-M-38510 — General Specifications for Micro-
circuits
MIL-STD-1051 — Sampling Procedures and Tables for
Inspections by Attributes
MIL-STD-23011 — Iron Nickel Alloys for Sealing to
Glass and Ceramics
MIL-STD-45204 — Gold Plating Electrodeposited
MIL-STD-87883 — Brazing
MIL-STD-883 — Test Methods and Procedures for
Microelectronics
3 Selected Definitions
blister bubble (ceramic) — any separation within the
ceramic which does not expose underlying ceramic
material.
blister bubble (metal) — any localized separation
within the metallization or between the metallization
and ceramic which does not expose underlying metal or
ceramic material.
1 ANSI, 1430, Broadway, New York, NY 10018
2 Military Standards, Naval Publications and Form Center, 5801
Tabor Avenue, Philadelphia, PA 19120
3 JEDEC, 2001 Eye Street, N.W., Washington, D.C. 20006
bond finger — a region of refractory metallization
within the package cavity intended for wirebonding to a
mirocircuit die pad.
braze — an alloy with a melting point equal to or
greater than 600°C.
burr — an adherent fragment of excess parent material
at the component edge.
chip-out — a region of ceramic missing from the
surface or edge of a package which does not go
completely through the package. Chip-out size is given
by its length, width, and depth from a projection of the
design plan-form (see Figure 1).
co-fired — a process or technology for manufacturing
products in which the ceramic and refractory
metallizations are fired simultaneously.
contact pad — that metallized pattern to which the
leadframe is brazed.
crack — a cleavage or fracture, internal or external.
die attach surface — a designated dimensional outline
area intended for die attach (see Figure 2).
foreign material — an adherent particle other than
parent material of that component.
layer — a dielectric sheet with or without metallization
that performs a discrete function as part of the package
construction.
lead offset — alignment of leads across the package.
peeling (flaking) — any separation from the basis
material that exposes the basis material.
projection — an adherent fragment of excess material
on the component surface.
pullback — the linear distance between the edge of the
ceramic and the first measurable metallization surface
(see Figure 3).
rundown — the linear distance down a vertical surface
from the top to the point of maximum metallization
overhang (see Figure 3).
seal area — a dimensional outline area designated for
either metallization or bare ceramic to provide a surface
area for lid sealing (see Figure 2).
terminal — metallization at the point of electrical
contact to package interior circuitry; also the brazing
surface for a lead.