semi合集-English.pdf - 第6499页

SEMI G80-0200 © SE MI 2000 7 single test pattern burst. The following nested loop outline describes the test flo w: for ampl it ude = 1V, 3V, 5V for direction = odd_ pins_drive_& _even_pins _co mpare to even _pins_dr…

SEMI G80-0200 © SEMI 2000 6

0 10ns 35ns

• 1 cycle: 3X = 30ns

•

1 cycle: 10X = 100ns

Total of 503 cycles. The intention of the last two cycles is

to define a period that is far beyond the minimum period.

Period resolution: 50ps

Minimum Period Cycle: 10ns

10ns to (10ns + 25ns) by 50ps

•

501 cycles:

For test_cycle = min_cycle to [min_cycle + 500*cycle

resolution] by cycle_resolution, 3Xmin_cycle, 10x min_cycle.

30ns

100ns

Example:

Figure 3

Test Cycle Example

10.3.4 Extended Delay Test — This test is used to

establish drive input to compare output timing accuracy

when timing generator delay values are programmed

beyond the length of the test cycle. Driver input delays

are programmed to occur in subsequent test cycles and

detected with compare delays originating in the corres-

ponding subsequent test cycle. The intention is the

same as Section 10.3.1 with the exception that edges

are programmed into a subsequent cycle. Conditions

such as formats and voltages have been reduced to keep

the amount of data collected down to a reasonable level.

10.3.4.1 The following nested loop outline describes

the test flow:

for amplitude = 3V

for direction =

odd_pins_drive_&_even_pins_compare to

even_pins_drive_&_odd_pins_compare

for test_cycle = min to 10*min by 0.1*min

for format = NR

for format_delay = test_cycle to max_delay by

0.25*test_cycle (max delay is beyond the cycle

boundary)

detect earliest occurrence of format

transition midpoint with the latest

compare pin using pattern expect

data shifted into the appropriate cycle

detect latest occurrence of format transition

midpoint with the earliest compare pin

using pattern expect data shifted into

the appropriate cycle

error = (latest occurrence - earliest

occurrence)

end delays

end format

end test cycles

end directions

end amplitude

10.3.5 Driver Z State Test — This test verifies the

timing accuracy of tester driver transitions from Z to

1/0 and from 1/0 to Z. Driver inputs are programmed to

transition to and from Z and 1/0 while being loaded

with 50 ohms terminated to drive 1 for Z to 0 and 0 to

Z, and 50 ohms terminated to drive 0 for Z to 1 and 1 to

(reference load C). The following nested loop

outline describes the test flow:

for amplitude = 3V

for direction =

odd_pins_drive_&_even_pins_compare to

even_pins_drive_&_odd_pins_compare

for test_cycle = 5*min_cycle

for format_delay = 50%

for format = NR

detect earliest occurrence of Z to low tran-

sition at scaled midpoint with compare pins

detect latest occurrence of Z to low tran-

sition at scaled midpoint with compare pins

error=(latest occurrence - earliest occurrence)

detect earliest occurrence of Z to 1 tran-

sition at scaled midpoint with compare pins

detect latest occurrence of Z to 1 transition

at scaled midpoint with compare pins

error = (latest occurrence - earliest occur-

rence)

detect earliest occurrence of 0 to Z transition

at scaled midpoint with compare pins

detect latest occurrence of 0 to Z transition at

scaled midpoint with compare pins

error = (latest occurrence - earliest occur-

rence)

detect earliest occurrence of 1 to Z tran-

sition at scaled midpoint with compare pins

detect latest occurrence of 1 to Z transition

at scaled midpoint with compare pins

error = (latest occurrence - earliest occur-

rence)

end format

end format_delay

end test_cycle

end direction

end amplitude

10.3.6 Multiple Period Test

— This is an optional test

to be run only if the ATE supports dynamic (or “on-the-

fly”) time set switching. This test intention is similar

to Section 10.3.1 and 10.3.4 (timing linearity and

extended delay tests) except that the test period and

delay changes are generated dynamically within a

7 Tying two drivers together or connecting a resistor to a logic point is

acceptable. Note: Load “C”: 50 ohms to low for driver z to high and high to z

transitions. And 50 ohms to high for driver z to low and low to z transitions.

8 This algorithm requires 64 time sets. If the equipment does not have 64 time

sets, adjust the algorithm to accommodate the amount available and note the

differences on the exception page, Appendix 3.

SEMI G80-0200 © SEMI 20007

single test pattern burst. The following nested loop

outline describes the test flow:

for amplitude = 1V, 3V, 5V

for direction =

odd_pins_drive_&_even_pins_compare to

even_pins_drive_&_odd_pins_compare

execute single pattern with the following

dynamic changes:

Test

Cycle

Drive

Format

Offset

Pulse

Width

Drive

Data

Compare

Offset

Expect

Data

min SBC 20% 33% 1 53% H

min SBC 20% 33% 1 86% L

min SBC 20% 33% 0 53% L

min SBC 20% 33% 0 86% H

min SBC 20% 33% 1 20% L

min SBC 20% 33% 0 20% H

64*min SBC 20% 33% 1 53% H

64*min SBC 20% 33% 1 86% L

64*min SBC 20% 33% 0 53% L

64*min SBC 20% 33% 0 86% H

64*min SBC 20% 33% 1 20% L

64*min SBC 20% 33% 0 20% H

2*min SBC 20% 33% 1 53% H

2*min SBC 20% 33% 1 86% L

2*min SBC 20% 33% 0 53% L

2*min SBC 20% 33% 0 86% H

2*min SBC 20% 33% 1 20% L

2*min SBC 20% 33% 0 20% H

63*min SBC 20% 33% 1 53% H

63*min SBC 20% 33% 1 86% L

63*min SBC 20% 33% 0 53% L

63*min SBC 20% 33% 0 86% H

63*min SBC 20% 33% 1 20% L

63*min SBC 20% 33% 0 20% H

32*min SBC 20% 33% 1 53% H

32*min SBC 20% 33% 1 86% L

32*min SBC 20% 33% 0 53% L

32*min SBC 20% 33% 0 86% H

32*min SBC 20% 33% 1 20% L

32*min SBC 20% 33% 0 20% H

detect earliest occurrence of format

transition midpoint with the latest

compare pin

detect latest occurrence of format transition

midpoint with the earliest compare pin

error = (latest occurrence - earliest occurrence)

end direction

end amplitude

Pairs of adjacent tester pins can be shorted together

with a minimum length interconnect on the

performance board.

A reference for the oscilloscope measurement is

required. That reference can be any signal

synchronized to the test system's timing. The

reference signal chosen should be consistent and

stable. Examples of this may be another tester pin or

master oscillator reference signal.

Pin n

Driver

Receiver

Pin n+1

Driver

Receiver

OTE 1: The user of this method may find improved

driver signal attributes using an open circuit

performance board, versus the shorted board

indicated here for Level 2 Drive Input Timing Error

data collection. On the other hand the shorted

performance board, using the driver as the signal

source, is a viable approach for the Compare Output

Timing Error Test. Regardless, the user may

optionally choose to use a pulse generator as the

signal source for the Compare Output Timing Error

test. The 50-ohm pulse generator must have edge

speeds that are comparable to the driver it is

replacing. Test setup conditions and the pulse

generator rise time employed must be documented on

the exception page (Appendix 3).

Oscilloscope

Short (See

OTE 1.)

Tester

Performance

board

Figure 4

Level 2 Verification

10.4 Level 2 Tests — The efficiency of data collection

with Level 1 tests may preclude isolation of certain

specification components. The self-analysis procedures

may also mask some error terms that contribute to other

specification components. Therefore, Level 2 modules

are intended to supplement Level 1 results by using

external instruments to distinguish individual

specification components and provide detailed analysis

SEMI G80-0200 © SEMI 2000 8

of potentially masked results. The use of external

instruments facilitates independent observation of

individual parameters, but requires physical movement

of a probe (unless automated with robotics), which

results in less efficient data collection. Reference

Figure 4.

10.4.1 Drive Input Timing Error Test — Since the

driver input timing error cannot be distinguished from

compare output timing error with Level 1 tests

external instrument must be used to isolate the driver

input timing error from compare output timing error.

An external instrument is also required to identify pin

to pin “skew” beyond adjacent pins, since Level 1 only

uses adjacent pin pairs for analysis. This requires

independent measurements of representative driver

input timing conditions. The reference for

measurement of driver input timing error is a high

bandwidth-digital sampling oscilloscope. Exhaustive

testing of all pins is impractical, so a reduced set of

representative conditions is used. A non-binary pin

sampling increment is used to ensure that traditional

binary architectural boundaries are crossed. The

tolerance for the driver input timing error test is ±

20ps

due to the tester/instrument interaction using a

generic measurement method. The following nested

loop outline describes the test flow:

for amplitude = 3V

for pin = 1 to n by 3

for test_cycle = min, 2*min, 3*min, 10*min

for format_delay = 50% of test cycle

for format = NR, RTZ, RTO, SBC

for all format transitions

detect midpoint of drive transition with

oscilloscope (averaging = 8)

error = (measured_delay - pro-

grammed_format_edge_time -

zero_reference_measurement)

end transitions

end format

end format_delay

end test_cycle

end pin

end amplitude

10.4.2 Compare Output Timing Error Test — Since

the compare output timing error cannot be distinguished

from driver input timing error with Level 1 tests, an

external reference must be used to isolate compare

output timing error from driver input timing error. This

requires independent measurement of representative

9 See APPENDIX 2, Section A2-1.3 and Appendix 2, Examples for an

explanation.

10 When recording measurements, data log all measurements as they are taken

from the measurement equipment and show the associated equipment tolerance

as a separate entity.

compare timing conditions. Each tester driver is used

to provide a synchronous reference signal by shorting

adjacent tester channels together on a performance

board with minimum, equal length interconnections.

The actual delay of the driver signal is verified with a

high bandwidth-digital sampling oscilloscope. (See

Figure 4.)

NOTE 2: If a signal reflection is present at the midpoint of the

observed signal (due to a long distance from the performance

board to the tester receiver), then the 25% point of the

reference driver waveform should be used, instead of the

midpoint - as specified below.

10.4.2.1 Exhaustive testing of all pins is impractical,

so a reduced set of representative conditions are used.

A non-binary pin sampling increment is used to ensure

that traditional binary architectural boundaries are

crossed.

10.4.2.2 The following nested loop outline describes

the test flow:

for amplitude = 3V

for pin = 1 to n by 3

for test_cycle = min, 2*min, 3*min, 10*min

for format_delay = 50% of test_cycle

for format = NR

for edge = rising, falling

detect midpoint of NR drive signal with

oscilloscope (averaging = 8)

detect midpoint of drive transition with

comparator (strobe compare mode)

error = (measured_delay - pro-

grammed_compare_delay -

zero_reference_measurement)

end edge

end format

end format_delay

end test_cycle

end pin

end amplitude

NOTE 3: Midpoint detection of the NR drive signal should be

done via a compare edge sweep technique.

10.4.3 Driver Transition Time Test — Since driver

transition time errors can be masked by compare timing

errors and comparator bandwidth limitations, an

external instrument is required to measure driver

transition time errors. The reference used for driver

transition time measurements is a high bandwidth-

digital sampling oscilloscope.

10.4.3.1 The tolerance for driver transition time

measurements is ± 150ps

due to the tester/instrument

11 This 150ps tolerance has been extended beyond 20ps due to level

sensitivities associated with oscilloscopes and typical bandwidth

variations in oscilloscope probes rendering transition time measurements

less accurate.