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SEMI G80-0200 © SE MI 2000 16 Compare Error MIN Valu e- MIN is the va lue al l compara tors are prog rammed to when t he firs t drive edge i s det ected. For a sw eep- Compar e edg es should be pro grammed f ar in advanc…

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SEMI G80-0200 © SEMI 200015
For reference see the following definitions taken from SEMI G79:
7.1.1 Input Edge Placement Accuracy — DUT input timing error comprised of input timing delay error, input timing jitter and
input transition time variation.
7.1.2 Output Edge Placement Accuracy — DUT output compare timing error comprised of output timing delay error and
output compare timing jitter.
Output Timing Delay Error –– time delay error at the detected midpoint of a 5V transition, with respect to an ideal delay
(NIST traceable reference), using any pin, any delay value, any compare timing edge,
window or strobe compare mode, expect H or L, positive or negative transition and any test
cycle length.
Conditions:
- measured with load circuit “off” or high impedance
- delays normalized to rising edge detected by pin 1, using strobe compare format, expect H, @ 0ns
- error normalized to the average of min & max of the error distribution
- input signal: 50-ohm source, 0–5V step, > 1V/ns, inserted at a zero length interconnect on the
DUT side of a standard performance board
Output Compare Timing Jitter –– short term (cycle to cycle) instability using any pin, any compare timing edge, window or
strobe compare mode, expect H or L. (NOTE: This document does not define a method
for Output Compare Timing Jitter.)
Conditions:
- error expressed as RMS value
- physical reference point is a zero length interconnect on the DUT side of a standard performance board
- jitter referenced to an independent synchronous trigger
7.1.3 Input to Output Timing Accuracy — relative time difference between the input delay timing and
output delay timing.
See SEMI G79.
Drive Input Edge Placement
Accuracy (See SEMI G79.)
(Verification = Sections
10.4.1, 10.4.3, and 10.4.4)
See SEMI G79.
B
A
Drive Input to Compare
Output Timing Accuracy
(See SEMI G79.)
(Verification – Section
10.3.1)
Compare Output Edge
Placement Accuracy (See
SEMI G79) (Verification –
Section 10.4.2, NOTE: This
does not include compare
j
itter.)
Overall Timing Accuracy
(+A, -B)
(Verification = Sections
10.4.1, 10.4.2, and 10.3.1)
Output timing delay
error.
See SEMI G79.
Output Delay Timing Error –– For another
machine, or a new spread for the same machine
as a result of a calibration.
See SEMI G79.
Figure 6
Overall Timing Accuracy (OTA)
SEMI G80-0200 © SEMI 2000 16
Compare Error
MIN Value- MIN is the value all
comparators are programmed to
when the first drive edge is
detected.
For a sweep- Compare edges
should be programmed far in
advance of the reference
signal allowing enough room
to detect the earliest
occurrence of a drive ed
g
e.
TIMING RELATIONSHIPS, DEFINITIONS & EXAMPLE RESULTS
DEFINITIONS-
Reference- The programmed value of the drivers
Drive to Compare Error- The difference between the average of min & max for Drive and the
average of min & max for Compare error.
RELATIONSHIPS & EXAMPLE RESULTS-
Negative Error: Reference - Min Value = 1000ps - 850ps = 150ps
Positive Error: Reference - Max Value = 1000ps - 1250ps = -250ps
Drive to Compare Error: Reference - [(Min Value + Max Value)/2] = 1000ps - [(850ps + 1250ps)/2] = -50ps
For a sweep- Compare edges
should be programmed fa
r
b
eyond the reference signal
allowing enough room to detec
t
the latest occurrence of a drive
d
MAX drive value- Detect the
latest occurrence of the drive edge
with the earliest compare edge
(last fail- Timing Linearity Test
10.3.1)
MIN drive value- Detect the
earliest occurrence of the drive
edge with the latest compare
edge (first pass- Timing
Linearity Test 10.3.1)
-100ps
Drive Edges
1000ps Drive
Reference
+100ps
-100
p
s +100
p
s
Drive Error
Drive
Reference
-100ps +100ps
Drive Edges
In this example:
Drive edge error = ±100ps
Compare edge error = ±100ps
Drive to Compare error = - 50ps
This example will illustrate how
numerical error values are
obtained.
Max Value- MAX is the value
all comparators are programmed
to when the last drive edge is
detected.
-100ps
1000ps
Drive
+100ps
N
OTE: All drive edges are
detected in parallel in pairs:
pin 1 & 2, 3 & 4,...n-1 & n.
N
OTE: All drive edges are
detected in parallel in pairs: pin 1
& 2, 3 & 4,...n-1 & n.
850
p
s
1050ps
950ps
1000ps Reference
-100
p
s +100
p
s
50
p
s
Drive
Reference
-100ps +100ps
First Pass
Min Value
Last Fail
Max Value
When the edges on all pins are
detected the drive to compare
error relationship will appear as
indicated here with associate
d
error values indicated.
1250ps
(Max value)
Sweep
Last fail
850ps
(Min value)
SweepCompare Edges
First pass
0ns
850ps
+100ps-100ps
+900ps
0ns
1250ps
Compare Edges
+100ps-100ps
1250ps
50ps
N
OTE: Additional information
related to this figure is contained
in Appendix 2.
Drive to Compare Edge Error
Figure 7
Level 1 Drive Edge Error = Compare Error
SEMI G80-0200 © SEMI 200017
Table 1 Data Collection Table for Levels 1 and 2
Test Number Channel Number Min. Value Max. Value
Section 10.3.1 Timing Linearity Test
(Drive Input Edge Placement)
m
to
n
Section 10.3.4 Extended Delay Test
(Compare Output Edge Placement)
m
to
n
Section 10.3.5 Drive Input Z Timing Error
(Z to 0 (Low))
m
to
n
Section 10.3.5 Drive Input Z Timing Error
(Z to 1 (High))
m
to
n
Section 10.3.5 Drive Input Z Timing Error
(0 (Low) to Z)
m
to
n
Section 10.3.5 Drive Input Z Timing Error
(1 (High) to Z)
m
to
n
L
E
V
E
L
O
N
E
Section 10.3.6 Multiple Period Test
(Optional- for on the fly timing)
m
to
n
Section 10.4.1 Drive Input Time Delay Error
(Drive Input Edge Placement)
m
to
n
Section 10.4.2 Compare Output Time Delay Error
(Compare Output Edge Placement)
m
to
n
Section 10.4.3 Drive Input Transition Time Variation m
to
n
Enter RMS value onlySection 10.4.4 Drive Input Timing Cycle Jitter
(Short term cycle to cycle period jitter)
m
to
n
Enter RMS value onlySection 10.4.5 High Speed Clock Self Trigger Cycle Jitter
(Short term cycle to cycle period jitter/clocks)
m
to
n
Enter RMS value only
L
E
V
E
L
T
W
O
Section 10.4.6 High Speed Clock Self Trigger Phase Jitter
(Short term phase /duty cycle jitter/clocks)
m
to
n
NOTE 6: This is a generic example of the data table needed to gather the data values for this timing analysis procedure. The
actual number of table entries will depend upon the number of tester pins under evaluation. The pins to be tested are represented
by the designation “m” to “n”. For Level 1 the application program is expected to fill in the minimum and maximum
measurements made for each pin and specified condition. For Level 2 the user will fill-in these data values via manual entry,
unless the application and implementation method employ automated/robotic operation.