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SEMI G5-87 © SEMI 1 980, 199 6 3 void, dielectric — An absence of screen printed ceramic f ro m a designated area greater than 0.76 mm (0.003") in diam eter. void, metallizatio n — An abs ence of refractory metalliz…

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SEMI G5-87 © SEMI 1980, 1996 2
i. Portion of external footprints connected to die
attach area and/or seal ring.
j. Terminal #1 position, internal and external.
k. Certification (optional).
l. Method of test and measurements.
m. Electrical, mechanical, environmental
requirements.
3. Reference to this specification
4. Any exception to print or specification
5 Dimensions and Permissi ble Variations
5.1 The dimensions of ceramic chip carriers shall
conform to those specified in the customer drawing,
and be within the outline of JEDEC Publication No. 95.
NOTE: A dimensioning scheme and measurement fixture are
under task force review.
5.2 Critical Material Parameters
5.2.1 Ceramic
5.2.1.1 Alumina, content 90% minimum.
5.2.1.2 Color — Dark or white.
5.2.2 Metallization
5.2.2.1 Refractory metallization.
5.2.2.2 Plating (if designated) per MIL-M-38510.
5.2.2.3 Nickel per QQ-N-290
5.2.2.4 Gold per MIL-STD-45204, Type III.
5.2.2.5 Gold Plating Quality see SEMI G8.
5.2.3 Braze per MIL-STD-7883.
5.2.4 Lead per MIL-STD-23011.
5.2.4.1 Iron Nickel Cobalt alloy per MIL-M-38510,
Type A.
5.2.4.2 Iron Nickel alloy per MIL-M-38510, Type B.
6 Functional Testing
The following tests are recommended for functional
evaluation of ceramic chip carriers. (The conditions of
acceptance to be negotiated between the customer and
the vendor.)
6.1 Die Attach
6.2 Pre-Seal Die Shear — (See Section 10.1.6.)
6.3 Wire Bond
6.4 Pre-Seal Bond Pull — (See Section 10.1.7.)
6.5 Seal
6.6 Environmental Test — (See Sections 10.1.1
through 10.1.13.)
6.7 Hermeticity — (See Section 10.1.14) Lid Torque
or Shear (for glass seal parts).
6.8 Post-Seal Bond Pull — (See Section 10.1.7.)
6.9 Post-Seal Die Shear — (See Section 10.1.6.)
7 Incoming Testing
7.1 Visual — (See Section 8.)
7.2 Dimensions
7.3 Functional — (See Section 6.)
7.4 Standard Tests
7.4.1 Electrical — (See SEMI G25.)
7.4.2 Gold Plating Quality — (See SEMI G8.)
7.4.3 Trim
7.4.4 Lead Integrity —(See Section 10.1.15.)
7.4.5 Solderability — (See Section 10.1.16.)
8 Visual
8.1 Applicable Definitions
blister (bubble) ceramic — Any separation within the
ceramic which does not expose underlying ceramic
material.
blister (bubble) metal — Any localized separation
within the metallization or between the metallization
and ceramic which does not expose underlying metal or
ceramic material.
burr — An adherent fragment of excess parent material
at the component edge.
chip — A region of ceramic missing from the surface or
edge of a package which does not go completely
through the package. Chip size is given by its length,
width, and depth from a projection of the design plan-
form (see Figure 2).
crack — A cleavage or fracture, internal or external.
die attach surface — See Figure 3.
discoloration — Any non-uniform color change of the
package plating.
foreign material — An adherent particle other than
parent material of that component.
LSI — Large scale integration.
SEMI G5-87 © SEMI 1980, 19963
void, dielectric — An absence of screen printed
ceramic from a designated area greater than 0.76 mm
(0.003") in diameter.
void, metallization — An absence of refractory
metallization, braze, or plating material from a
designated area greater than 0.076 mm (0.003") in
diameter.
8.2 Visual Criteria — (10× magni fication) (See
Section 8.1.)
8.2.1 Ceramic — Unmetallized Surfaces
8.2.1.1 Cracks — None allowed per MIL-M-38510,
Method 1014.
8.2.2 Chips
8.2.2.1 Corner — 0.762 mm (0.030") × 0.762 mm
(0.030") × one tape layer thickness, maximum.
8.2.2.2 Edge — 2.54 mm (0.100") × 0.762 mm
(0.030") × one tape layer thickness, maximum.
8.2.2.3 Chips cannot encroach upon seal area, or
contact pad, or expose any buried metallization.
8.2.3 Burrs, Projections, and Blisters
8.2.3.1 Top Plane, Excluding Seal Area — 0.102 mm
(0.004") maximum.
8.2.3.2 Seal Area — 0.025 mm (0.001") maximum.
8.2.3.3 Heat Exchanger Attach Area — 0.076 mm
(0.003") maximum (if designated).
8.2.3.4 Contact Surface — 0.051 mm (0.002")
maximum.
8.2.3.5 Edges — 0.152 mm (0.006")
8.2.3.6 Burrs, projections, and blisters must fit within
the outline tolerances.
8.2.4 Camber — Ceramic of 0.1 mm/25.4 mm (0.004
inch/inch), maximum. None to be specified less than
0.076 mm (0.003") along any planar dimension of the
part.
8.2.5 Flatness — See table below:
Table 1 Flatness
Flatness: Seal Area: Seal Ring Size Flatness (TIR)
0–6.35 mm (0"–0.250") 0.051 mm max. (0.002")
6.37–12.7 mm (0.251"–0.500") 0.076 mm max. (0.003")
12.72 –25.4 mm (0.501"–1.000") 0.101 mm max. (0.004")
25.42 mm and up (1.001") 0.004 in/in
8.3 Ceramic Metallized Surfaces
8.3.1 Voids
8.3.1.1 Seal Area — maximum of 3 voids permitted.
No more than two voids per side of 0.010" diameter
maximum each. Any two voids must be separated by
0.030" (0.762 mm) minimum, not to degrade the seal
width by more than 25%.
8.3.1.2 Footprint — Two voids per pad 0.254 mm
(0.010") diameter maximum. A contiguous path must
never be reduced by more than 1/3 the minimum design
width.
8.3.1.3 Wire Bond Fingers — A void-free area 0.254
mm (0.010") × 0.254 mm (0.010") or as defined by the
customer drawing.
8.3.1.4 Heat Exchange Attach Area — (if designated)
The major dimension of a void shall not exceed 0.508
mm (0.020") and all voids must be separated by 0.762
mm (0.030"). Total void area to be equal or less than
10%.
8.3.1.5 Die Attach Surface — Three voids of 0.010"
diameter are the maximum allowed separated by 0.030"
minimum.
NOTE: Voids within 0.015" of a cavity wall 0.381 mm are
excluded from this requirement.
Table 2 Die Attach Area Flatness Limits
Die Attach Pad Dimension TIR Flatness
0-12.7 mm (0–0.500") 0.51 mm (0.002" max.)
12.72–19.5 mm (0.501"–
0.750")
0.088 mm (0.0035" max.)
8.3.1.6 Internal Metallization — Voids shall not break
continuity between wire bond fingers and the
corresponding contact pad. The user may specify
additional resistance and capacitance parameters for
each application.
8.3.2 Burrs and Projections — Shall not exceed the
specification of Table 3.
Table 3 Maximum Height of Burrs and Projections
Maximum
Inches Height mm
Wire Bond Finger Area 0.001 (0.025)
Seal Area 0.001 (0.025)
Die Attach Surface 0.001 (0.025)
Contact Pad 0.002 (0.051)
Heat Exchanger Attach Area 0.003 (0.076)
SEMI G5-87 © SEMI 1980, 1996 4
8.3.3 Pattern Definitions (Cavity Packages) — (See
Figure 4.)
8.3.3.1 Seal Plane Rundown — internal cavity — Not
to exceed 25% of the cavity layer thickness.
8.3.3.2 External to the Cavity — Separation shall not
be less than 0.254 mm (0.010") or 50% of the design
width, whichever is less.
8.3.3.3 Wire Bond Finger Pullback — Not to exceed
maximum from the cavity edge. The minimum exposed
lead length must meet the dimension per applicable
drawing.
8.3.3.4 Wire Bond Finger Rundown — Not to exceed
25% of the ceramic layer thickness or 0.127 mm
(0.005"), whichever is smaller.
8.3.4 Pattern Separation — Minimum shall not be
reduced by more than 50% of the design.
8.4 Lead Attachment
8.4.1 Voids in Braze — 66% of the braze fillet must be
void-free.
8.4.2 Lead Alignment — Misalignment leads to braze
pads — The leads shall not overhang braze pads.
8.4.2.1 Lead Offset — To be specified on user
drawing. Lead center lines must be aligned to within
.178 mm (.007").
8.4.2.2 Lead-to-Lead Misalignment — To exceed ±
10% of nominal lead spacing.
8.4.2.3 Dimensional Criteria — To be specified on
user drawing.
9 Sampling
Sample sizes must meet requirements of MIL-STD-105
or MIL-M-38510 as agreed to between vendor and
customer. Single, double, or multiple samples may be
used.
10 Test Methods
10.1 Mechanical, Electrical, and Thermal Test
Methods — Per MIL-STD-883, unless otherwise noted.
10.1.1 Gold plating thickness shall conform to MIL-
STD-45204. Gold thickness may be determined using
the Beta Backscatter Radiation Method or X-Ray
Fluorescence.
10.1.2 Nickel plating shall conform to MIL-STD-
45204. Nickel thickness may be determined using the
Beta Backscatter Radiation Method.
10.1.3 Seal Ring Flatness — See SEMI G6.
10.1.4 Electrical Trace Resistance — See SEMI G25.
10.1.5 Gold Plating Quality — See SEMI G8.
10.1.6 Die Shear — Destructive — Method 2019.
10.1.7 Wire Bond — Method 2011, Condition D.
Reject for bonds which cause plating to lift from the
base metal of the die attach surface or bonding fingers.
10.1.8 Temperature Cycle — Method 1010, Condition
C.
10.1.9 Thermal Shock — Method 1011, Condition C.
10.1.10 Constant Acceleration — Method 2001,
Condition E.
10.1.11 Mechanical Shock — Method 2002, Condition
B.
10.1.12 Insulation Resistance — Method 1003.
10.1.13 Internal Water Vapor Content — Method
1018.
10.1.14 Hermeticity — Method 1014, Conditions A,
B, and C. The hermetic integrity of the package must be
maintained after all environmental testing.
10.1.15 Lead Integrity — Method 2004, Condition B.
10.1.16 Solderability — 2003.
10.1.17 Moisture Resistance Testing — Method 1004.
11 Packaging and Marking
11.1 Packaging — Containers selected shall be strong
enough, and suitably designed, to provide maximum
protection against crushing, spillage, and other forms of
damage to the container or its contents. Containers shall
afford protection of the contents to contamination from
exposure to excessive moisture or oxidation by gases.
Packaging materials shall be so selected to prevent any
contamination of the ceramic component parts with
paper fibers or organic particles. Regardless of
packaging, all parts should be cleaned before testing or
use.
11.2 Marking — The outer containers shall be clearly
marked identifying:
1. Vendor Part #
2. Customer Part #
3. Quantity
4. Date
5. Vendor Lot #
6. User P.O. number (optional)
7. Drawing number (optional)