semi合集-English.pdf - 第4973页

SEMI M11-0704 © SEMI 1988, 2004 30 ITEM p/p - EPITAXIAL CIRCUIT WAFER (DRAM) p/p + EPITAXIAL CIRCUIT WAFER (Logic/ DRAM) p/p ++ EPITAXIAL CIRCUIT WAFER (Logic) 8.3 Loca lized Light Scat terers - Only particles for epitax…

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SEMI M11-0704 © SEMI 1988, 2004 29
ITEM p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPITAXIAL
CIRCUIT WAFER
(Logic)
5.4 Extrinsic Gettering Treatment user/supplier user/supplier user/supplier
5.5 Backseal none None or as
user/supplier
agreement
None or as
user/supplier
agreement
5.6 Annealing None or as
user/supplier
agreement
None or as
user/supplier
agreement
None or as
user/supplier
agreement
6.0 MECHANICAL CHARACTERISTICS
6.1 Diameter 300 ± 0.2 mm
or
200 ± 0.2 mm
300 ± 0.2 mm
or
200 ± 0.2 mm
300 ± 0.2 mm
or
200 ± 0.2 mm
6.2 Diameter Notch Dimensions
6.2.1 Notch Depth 1 +0.25,-0.00 mm 1 +0.25,-0.00 mm 1 +0.25,-0.00 mm
6.2.2 Notch Angle 90 +5,-1 degrees 90 +5,-1 degrees 90 +5,-1 degrees
6.3 Notch Orientation <110> ± 1° <110> ± 1° <110> ± 1°
6.61 Edge Profile* per SEMI M1 per SEMI M1 per SEMI M1
6.6.2 Edge Surface Finish Polished * Polished * Polished *
6.7 Thickness 775 ± 25 µm*
[300 mm diameter]
or
725 ± 20 µm*
[200 mm diameter]
775 ± 25 µm*
[300 mm diameter]
or
725 ± 20 µm*
[200 mm diameter]
775 ± 25 µm*
[300 mm diameter]
or
725 ± 20 µm*
[200 mm diameter]
6.7.1 Thickness Variation (9-Point TTV) NS NS NS
6.72 Thickness Variation (GBIR) " 3 µm " 3 µm " 3 µm
6.9 Surface Orientation 100 100 100
6.10 Bow NS NS NS
6.11 Warp
(only process control data required)
" 50 µm " 50 µm for wafers
without backseal
" 100 µm for wafers
with backseal
" 50 µm for wafers
without backseal
" 100 µm for wafers
with backseal
6.12 Sori NS NS NS
6.13 Flatness/Global NS NS NS
6.14B Flatness/Site (See Note 4) SFSR " 0.13 µm SFSR " 0.13 µm SFSR " 0.13 µm
7.0 FRONT SURFACE CHEMISTRY
7.1 Surface Metal Contamination
See Note 9
Sodium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Aluminum " 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
Potassium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Chromium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Iron " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Nickel " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Copper " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
Zinc " 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
" 1 × 10
11
/cm
2
Calcium " 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
" 1.3 × 10
10
/cm
2
8.0 FRONT SURFACE CRITERIA
8.1A Scratches (macro) none none none
8.1B Scratches (micro) " 10 mm (total length) " 10 mm (total length) " 10 mm (total length)
SEMI M11-0704 © SEMI 1988, 2004 30
ITEM p/p
-
EPITAXIAL
CIRCUIT WAFER
(DRAM)
p/p
+
EPITAXIAL
CIRCUIT WAFER
(Logic/DRAM)
p/p
++
EPITAXIAL
CIRCUIT WAFER
(Logic)
8.3 Localized Light Scatterers
- Only particles for epitaxial wafers
- Sizes are PSL equivalents
300 mm:
" 200 @ ! 0.09 µm
or
" 112 @ ! 0.12 µm
(See note 5.)
300 mm:
" 200 @ ! 0.09 µm
or
" 112 @ ! 0.12 µm
(See note 5.)
300 mm:
" 200 @ ! 0.09 µm
or
" 112 @ ! 0.12 µm
(See note 5.)
200 mm:
" 89 @ ! 0.09 µm
or
" 50 @ ! 0.12 µm
(See note 5.)
200 mm:
" 89 @ ! 0.09 µm
or
" 50 @ ! 0.12 µm
(See note 5.)
200 mm:
" 89 @ ! 0.09 µm
or
" 50 @ ! 0.12 µm
(See note 5.)
8.4 Edge Chips none none none
8.5-8.16 OTHER none none none
9.0 BACK SURFACE CRITERIA
9.1 Edge Chips none none none
9.2-9.5 OTHER none none none
9.6 Roughness NS NS NS
9.7 Brightness (Gloss) 60° angle of incidence,
referenced to a mirror polished wafer.
NOTE: Double-side polish process
preferred
! 80%. ! 80% Applies to
wafers without
backseal only.
! 80% Applies to
wafers without
backseal only.
TBD Localized Light Scatterers (See Note 6.) NS NS NS
TBD Scratches (Macro) none none none
TBD Scratches (Micro) Cumulative Length
" 10% of the Wafer
Diameter
Cumulative Length
" 10% of the Wafer
Diameter
Cumulative Length
" 10% of the Wafer
Diameter
11.0 ADDITIONAL EPITAXIAL LAYER CHARACTERISTICS
11.1 Conductivity Type/Structure p/p- p/p+ p/p++
11.2 Primary Dopant Boron Boron Boron
11.3 Silicon Source Gas NS NS NS
11.4 Epi Growth Method NS
(see item 5.3)
NS
(see item 5.3)
NS
(see item 5.3)
11.5 Carrier Density Range - Must be met at all
points on the wafer surface inside the edge
exclusion (See Note 11.)
User/supplier
agreement
User/supplier
agreement
User/supplier
agreement
11.6 Layer Thickness (Target Value at Wafer
Center and Tolerance)
Target: user/supplier
agreement
Tolerance: ± 5%
Target: user/supplier
agreement
Tolerance: ± 5%
Target: user/supplier
agreement
Tolerance: ± 5%
11.7 Thickness Variation (within wafer per
SEMI M11)
10% 10% 10%
11.8 Transition Width User/supplier
agreement
User/supplier
agreement
User/supplier
agreement
11.9 Layer Flat Zone User/supplier
agreement
User/supplier
agreement
User/supplier
agreement
13.1 Stacking Faults (See Note 7.) < 0.012/cm
2
< 0.012/cm
2
< 0.012/cm
2
TBD Large Area Defects (LAD’s)
(See Note 7.)
< 0.006/cm
2
< 0.006/cm
2
< 0.006/cm
2
13.2 Slip/Dislocations (See Note 8.) none none none
13.5 -
13.13
OTHER (see 13.1) (see 13.1) (see 13.1)
SEMI M11-0704 © SEMI 1988, 2004 31
NOTE 1: * indicates substrate specification.
NOTE 2: NS is the abbreviation for Not Specified.
NOTE 3: Non-destructive metrology did not exist at the time this document was approved.
NOTE 4: The site size is 25 mm × 32 mm. Partial sites are included. The metrology was being developed at the time this document was being
balloted.
NOTE 5: These values are mathematically consistent. The 0.09 µm count limit was transformed using draft international standard: ISO 14644-1
which follows the equation: 112 counts per wafer
= 200 counts per wafer
/(0.12 µm /0.09 µm)
2
.
NOTE 6: The process control capability is expected to be: " 500 @ ! 0.25 µm.
NOTE 7: Large Area Defects (LAD’s) are surface imperfections or particles that have geometry with at least one side or diameter that is a
minimum of 1 micron in length .
NOTE 8: Tested per SEMI MF1726; a depth < 100 nm is acceptable.
NOTE 9: Only process control data is required. Data not required on Certificate of Compliance.
NOTE 10: The first column under item references SEMI M18. M18 was in the process of substantial revision at the time this documented was
balloted. Many M18 line references remain to be determined. TBD is the abbreviation for “to be determined”.
NOTE 11: The intent in specifying carrier density using a range, rather than the center nominal with tolerance accompanied by a wafer variation
limit, is to minimize the importance of edge variations and to emphasize meeting the range of carrier density as it is allowed by the process and
the designers.
Table 10 Guide for the Specification of 90 nm
Design Rule Silicon Epitaxial Wafers with DSP Substrates
ITEM (See Note 1)
p/p
−
EPITAXIAL
WAFER
p/p
+
EPITAXIAL
WAFER
p/p
++
EPITAXIAL
WAFER
1.0
SUBSTRATE GENERAL CHARACTERISTICS (See Note
１)
1.1 Growth Method Cz or MCz
1.2
Crystal Orientation {100}
1.3
Crystal Orientation/Tolerance ±1°
1.4
Substrate Conductivity Type
p
−
p
+
p
++
1.5 Dopant Boron
1.6 Nominal Edge Exclusion (Note 2) 2 mm (300 mm) or 3 mm (200 mm)
2.0
SUBSTRATE ELECTRICAL CHARACTERISTICS
2.1
Substrate Resistivity (Center Point)
0.8−15 Ω·cm 0.01−0.02 Ω·cm
0.005−0.010 Ω·cm
2.2
Substrate Radial Resistivity Variation
(See Note 3.)
≤ 20%
3.0
CHEMICAL CHARACTERISTICS
3.1 Oxygen Concentration (Center)
supplier-purchaser
agreement
(See Notes 4 & 5)
supplier-purchaser agreement (See Notes 4 &
6)
supplier-purchaser
TBD Oxygen Concentration Tolerance (Center)
supplier-purchaser agreement
3.2 Radial Oxygen Variation
supplier-purchaser agreement
10 mm from Edge (See Note 7)
3.3 Carbon Concentration
" 0.5 ppma
（Background,
See Notes 3 & 4）
" 0.5 ppma
（Background, See Notes 3, 4 & 8）
4.0
STRUCTURAL CHARACTERISTICS
4.1 Dislocation Etch Pit Density
4.2 Slip
4.3 Lineage
supplier-purchaser agreement