semi合集-English.pdf - 第4833页

SEMI M1-0305 © SEMI 1978, 2005 9 5.3.1 Lot acceptanc e procedures. 5.3.2 Certification ( if required). 5.3.3 Packi n g and s hipping container la beling re quirements. 5.4 Finally, many other characteristics may be speci…

SEMI M1-0305 © SEMI 1978, 2005 8

50441/1 — Determination of the Geometric Dimensions of Semiconductor Slices: Measurement of Thickness

50441/2 — Determination of the Geometric Dimensions of Semiconductor Slices: Testing of Edge Rounding

50441/3 — Measurement of the Geometric Dimensions of Semiconductor Slices; Determination of Flatness

Deviation of Polished Slices by Means of Multiple Beam Interference

50441/4 — Determination of the Geometrical Dimensions of Semiconductor Slices: Diameter and Flat Depth of

Slices

50443/1 — Recognition of Defects and Inhomogenities in Semiconductor Single Crystals by X-Ray Topography:

Silicon

50445 — Contactless Determination of the Electrical Resistivity of Semiconductor Wafers with the Eddy Current

Method

3.6 ANSI Standards

ANSI/ASQC Z1.4 — Sampling Procedures and Tables for Inspection by Attributes

ANSI/EIA 556-B — Outer Shipping Container Standard

3.7 ISO Standard

ISO 14706 — Surface chemical analysis — Determination of surface elemental contamination on silicon wafers by

total reflection X-ray fluorescence spectroscopy (TXRF)

NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.

4 Terminology

4.1 Terms and acronyms associated with silicon wafers and silicon technology are listed and defined in SEMI M59.

5 Ordering Information

5.1 Purchase orders for silicon wafers furnished to this specification shall include the following items. These items

are indicated on the Silicon Wafer Specification Format for Order Entry, Parts 1 and 2, shown in Table 1 with a 

symbol in the left-most column.

5.1.1 Growth Method.

5.1.2 Crystal Orientation.

5.1.3 Conductivity type.

5.1.4 Dopant.

5.1.5 Wafer surface orientation.

5.1.6 Resistivity.

5.1.7 Diameter.

5.1.8 Fiducial dimensions and orientation.

5.1.9 Edge profile.

5.1.10 Thickness and tolerance.

5.2 In addition, the purchase order must indicate the test method to be used in evaluating each of those items for

which alternate test procedures exist.

5.3 The following items must also be included in the purchase order:

5 American National Standards Institute, New York Office: 25 West 43rd Street, New York, NY 10036, USA. Telephone: 212.642.4900, Fax:

212.398.0023, Website:

www.ansi.org

6 International Organization for Standardization, ISO Central Secretariat, 1, rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland.

Telephone: 41.22.749.01.11; Fax: 41.22.733.34.30 Website:

www.iso.ch

SEMI M1-0305 © SEMI 1978, 2005 9

5.3.1 Lot acceptance procedures.

5.3.2 Certification (if required).

5.3.3 Packing and shipping container labeling requirements.

5.4 Finally, many other characteristics may be specified in purchase orders for silicon wafers.

5.4.1 These shall be selected from the other items listed in the Silicon Wafer Specification Format for Order Entry,

Parts 1 and 2 (see Table 1).

5.4.1.1 The parameter values provided in the requirements tables in §6 may be used to identify appropriate values in

the specification without selecting a value for each line. However, even if these requirements table values are used,

the desired test methodology must be selected in accordance with ¶5.2.

5.4.2 It is essential that all choices for the items selected to be specified be made in order not to have unspecified

parameters that would lead to surprises between supplier and customer. This is particularly important in the

specification of wafer site flatness, for which a variety of parameters must be selected as outlined in Appendix 1.

5.4.3 Of the various items listed, the following (listed in the order in which they appear in Table 1) are most often

selected, especially for wafers to be used for advanced integrated circuit manufacture:

 nominal edge exclusion (to define the fixed quality area),

 structural characteristics,

 wafer ID marking,

 total thickness variation (TTV or GBIR),

 warp (and sometimes bow or sori),

 site flatness (SFQR), and

 localized light scatterers (LLS).

6 Requirements

6.1 General Characteristics

6.1.1 The crystal growth method shall be modified Czochralski (Cz), float zone (FZ), or magnetic Czochralski

(MCz) as specified on the purchase order. In some cases, the supplier is given the option of selecting Cz or MCz.

6.1.1.1 If the Cz or MCz method is used for crystal growth, it may be permissible to utilize refined (previously

melted) polysilicon in the growth charge; when this is the case, the appropriate box should be checked..

6.1.2 The crystal orientation shall be as specified on the purchase order. Usually either (100) or (111) is specified,

but (110) is sometimes specified for polished wafers to be used for making SOI wafers. Occasionally, another

orientation, such as (311) or (511), is specified.

6.1.3 The conductivity type shall be either n or p.

6.1.4 The dopant shall be specified to match the conductivity type. In general, boron (B) is used for p-type

material, while phosphorus (P) is most commonly used for n-type material. For some applications, antimony (Sb) or

arsenic (As) are used to obtain

n-type wafers. For high power applications, neutron transmutation doping is often

used to obtain high resistivity n-type wafers.

6.1.5 The nominal edge exclusion, EE, specifies the diameter of the fixed quality area (FQA), which is given by the

nominal diameter minus 2·EE (see Figure 1). This quantity provides a center-referenced property.

SEMI M1-0305 © SEMI 1978, 2005 10

Table 1 Silicon Wafer Specification Format for Order Entry, Parts 1 and 2

Part 1 General Information

ITEM INFORMATION Date:

Customer Name

Purchase Order Number

Line Number

Item Number

General Specification Number

Revision Level

Part Number/Revision

Part 2 Polished Wafer or Substrate

ITEM SPECIFICATION MEASUREMENT METHOD

2-1. GENERAL CHARACTERISTICS (Note that  indicates a required item for which a value or choice must be indicated in order to minimally specify a silicon wafer.)



2-1.1 Growth Method [ ]Cz; [ ]FZ; [ ]MCz; [ ]Supplier option of Cz or MCz

2-1.2 Use of Refined Polysilicon [ ]Permitted; [ ]Not permitted



2-1.3 Crystal Orientation [ ](100); [ ](111); [ ](110); [ ]Other: (specify) ( )

[ ]SEMI MF26 (X-Ray); [ ] SEMI MF26 (Optical);

[ ]JEITA EM-3501; [ ]DIN 50433/1; [ ]DIN 50433/2;

[ ]DIN 50433/3; [ ]Other: (specify)____________



2-1.4 Conductivity Type [ ]p; [ ]n

[ ]SEMI MF42; [ ]JIS H 0607; [ ]DIN 50432;

[ ]Other: (specify)______



2-1.5 Dopant

[ ]B; [ ]P; [ ]Sb; [ ]As; [ ]Neutron Transmutation Doped;

[ ]Other: (specify) ______

2-1.6

Nominal Edge Exclusion

(See Figure 1)

[ ]2 mm; [ ]3 mm; [ ]5 mm; [ ]Other: (specify)_______mm

2-1.7 Co-dopant in Crystal

[ ]None; [ ]Nitrogen; [ ]Carbon; [ ]Nitrogen and Carbon;

[ ]Argon; [ ]Other: (specify)__________



2-1.8 Wafer Surface Orientation

(with respect to crystal

orientation, see item 2-1.3)

[ ]On-orientation: [ ]0.00 ± 1.00; [ ]0.00  _____

[ ]Off-orientation: [ ]0.6  0.4 [ ]2.50 ± 0.50;

[ ]4.00 ± 0.50; [ ]_____  _____

[ ]SEMI MF26 (X-Ray); [ ] SEMI MF26 (Optical);

[ ]JEITA EM-3501; [ ]DIN 50433/1; [ ]DIN 50433/2;

[ ]DIN 50433/3; [ ]Other: (specify)_____________

2-1.9 Orthogonal Misorientation

(See Figure 2)

[ ] 5 max; [ ]Other: [ ], max