semi合集-English.pdf - 第7300页

SEMI MF1049-0304 © SEMI 2003, 2004 4 NOTE 6: The percentage of the wafer covered may be determined with the use of the universal waf er grid specified in SEMI M17 that divides the wafer into 1000-area elements. If the un…

100%1 / 7923
SEMI MF1049-0304 © SEMI 2003, 2004 3
add 2 parts hydrofluoric acid (HF) to 1 part chromic
acid solution and 1.5 parts water by volume. Prepare
and mix in HF-proof beakers.
8.3.4 The specified chemicals shall have the following
nominal assay:
Chromium trioxide >98.0%
Hydrofluoric acid, concentrated 49 ± 0.25%
8.3.5 The chemicals used in this evaluation procedure
are potentially harmful and must be handled in an acid
exhaust fume hood, with utmost care at all times.
9 Sampling
9.1 Select wafers to represent the lot to be tested as
specified in producer-consumer agreements.
10 Specimen Preparation
10.1 In most instances this practice may be used for
polished or epitaxial wafers as they are received, but if
cleaning is required, the parties using this practice must
establish a mutually acceptable cleaning procedure
prior to etching.
11 Procedure
11.1 Handle wafers only with a clean, nonmetallic
pickup tool or automated transfer unit to avoid
scratching or contaminating the surface.
11.2 Oxidize the wafers by the thermal sequence listed
in Table 1.
NOTE 5: Large diameter furnaces may have difficulty in
duplication of this process. Rapid thermal processing is an
acceptable alternative.
11.2.1 Preheat the furnace to the push temperature.
11.2.2 Load the specimen wafers into the wafer boat,
being careful to avoid binding, scratching, or
contamination.
Table 1 Shallow Pit Oxidation Procedure
Step Function Conditions
Ambient 1% O
2
, 99% N
2
Temperature 950° C
Push (Load)
Push Rate 60 cm/min.
Ambient 1% O
2
, 99% N
2
Temperature 950° C
Oxidation
Time 7 min
Ambient 1% O
2
, 99% N
2
Temperature 950° C
Pull (Unload)
Pull Rate 60 cm/min.
11.2.3 Insert the boat into the hot zone at the rate called
for in Table 1. The wafer boat shall be centered in the
uniform hot zone.
11.2.4 Follow the oxidation and pull procedures as
specified in Table 1.
11.2.5 Because silicon wafers and quartz accessories
are extremely hot when they are removed from the
oxidation furnace, allow the materials adequate time to
cool before handling.
11.3 Transfer the room temperature wafers from the
quartz boat to a wafer holder using the pickup tool or
automated transfer unit.
11.4 Remove the thermal oxide layer using
hydrofluoric acid for 2 min followed by water rinse and
dry, using the spin dryer, if available.
11.4.1 Caution — Hydrofluoric acid solutions, used
here and for etching, are particularly hazardous and
specific preventive measures must be strictly observed.
Safety or protective gear should be worn while handling
acid solutions. Safety requirements vary, but the
essentials are: acid sink and personnel covering
including plastic gloves, safety glasses, face shield, acid
gown, and shoe covers. Hydrofluoric acid solutions
should not be used by anyone who is not familiar with
the specific preventive measures and first aid treatments
given in the appropriate Material Safety Data Sheet.
11.5 Etch the wafers for 2 minutes in an adequate
amount of Schimmel etch appropriate for the wafer
resistivity (see Sections 8.3.2 and 8.3.3). If the defect
etch pits are too small to distinguish, increase the etch
time up to 5 min.
11.5.1 Warning: Chromic acid, contained in the defect
etch solutions, should not be released into drains that
lead directly to domestic sewers. Chromates are an
extreme eco-hazard and must be first treated by reduc-
tion to the trivalent form. Chromic acid is a strong
oxidizing agent and should not be allowed to contact
organic solvents or other easily oxidized materials.
11.6 Quickly transfer the loaded wafer holder into a
water bath to rinse the wafers.
11.7 Dry the wafers, using the spin dryer, if available.
12 Evaluation
12.1 View the wafers at 1× magnification under the
high-intensity, narrow-beam light source in a dark
hood. If haze is observed, further examine the etched
wafer under a minimum of 200× magnification to
establish if the haze is due to shallow etch pits. If no
shallow etch pits are seen, record the wafer as being
free of shallow etch pits.
SEMI MF1049-0304 © SEMI 2003, 2004 4
NOTE 6: The percentage of the wafer covered may be
determined with the use of the universal wafer grid specified
in SEMI M17 that divides the wafer into 1000-area elements.
If the universal wafer grid is used, record the size of the edge
exclusion or the fixed quality area used. A1.6-mm peripheral
ring on a 125-mm diameter wafer represents 5% of the wafer
area.
12.2 Determine the level of haze present on the surface
from Table 2.
Table 2 Haze Level Classification
Level % of Wafer Area
A 0–5
B 5–25
C 25–75
D 75–100
12.3 Optional Estimation of Shallow Etch Pit Density
— If it is desired to estimate the shallow etch pit
density, use the procedure in Related Information 1.
13 Report
13.1 Report the following information:
13.1.1 Date of test, laboratory and operator
identification,
13.1.2 Identification of wafer lot,
13.1.3 Identification of the test wafer(s) (including
conductivity type, orientation, diameter, growth
method, and back surface condition),
13.1.4 Level of haze for each wafer tested, and
13.1.5 A diagram showing the location and distribution
of areas of high shallow etch-pit density, and, if
estimates of shallow etch-pit density are made,
locations of the count positions.
13.2 If the shallow etch-pit density was estimated on
one or more wafers, also report the following
information of each wafer tested:
13.2.1 Magnification used in the test,
13.2.2 Average estimated shallow etch-pit density, and
13.2.3 Maximum and minimum measured shallow
etch-pit density, if more than one count position was
employed.
14 Keywords
14.1 epitaxial; oxidation; preferential etch; saucer pit;
shallow etch pit; silicon
SEMI MF1049-0304 © SEMI 2003, 2004 5
RELATED INFORMATION 1
METHOD FOR ESTIMATION OF SHALLOW ETCH PIT DENSITY
NOTICE: This related information is not an official part of SEMI MF1049. It was developed as part of the
development of the document. This related information was approved for publication by full letter ballot on
December 4, 2003.
R1-1 Procedure
R1-1.1 Examine the wafer under magnification in the
range from 200 to 1000× to distinguish between etching
artifacts and shallow etch pits.
R1-1.2 Place the wafer on the microscope stage.
R1-1.3 Position the specimen so as to view the area of
interest on the etched wafer surface. Choose the area to
be viewed to include a high density of haze.
R1-1.4 Adjust the magnification so that up to 100
shallow etch pits are seen in the field of view. If more
than 100 shallow etch pits are in the field of view at
maximum magnification, report the shallow etch pit
density as “Too high to count.”
R1-1.5 Calculate the area of the field of view from its
diameter as determined to ± 1 µm with a stage
micrometer.
R1-1.6 Count and record the number of shallow etch
pits in the field of view. Count as one defect, those
defects that converge or overlap except when the etch
pits are well defined and are individually distin-
guishable.
R1-1.7 Determine the estimate of the shallow etch-pit
density by dividing the number of etch pits counted by
the area of the field of view.
R1-1.8 If more than one area is counted, compute the
average shallow etch-pit density for the wafer by
dividing the sum of the shallow etch-pit densities
estimated by the total number of counting positions.
R1-2 Precision and Bias
R1-2.1 Precision — Because this optional method is
intended for use only for qualitative estimates of the
area of a wafer covered by haze due to shallow etch pits
and the shallow etch-pit density, no interlaboratory
evaluation of this optional method has been conducted
for the purposes of determining its expected
repeatability or reproducibility.
R1-2.2 Bias — No standards exist against which the
bias of this optional method can be evaluated.
NOTICE: SEMI makes no warranties or representa-
tions as to the suitability of the standards set forth
herein for any particular application. The determination
of the suitability of the standard is solely the
responsibility of the user. Users are cautioned to refer
to manufacturer' s instructions, product labels, product
data sheets, and other relevant literature, respecting any
materials or equipment mentioned herein. These
standards are subject to change without notice.
By publication of this standard, Semiconductor
Equipment and Materials International (SEMI) takes no
position respecting the validity of any patent rights or
copyrights asserted in connection with any items
mentioned in this standard. Users of this standard are
expressly advised that determination of any such patent
rights or copyrights, and the risk of infringement of
such rights are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.