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SEMI M11-0704 © SEMI 1988, 2004 1 SEMI M11-0704 SPECIFICATIONS FOR SILICO N EPITAXIAL WAFERS FOR INTEGRATED CIRCUIT (IC) APPLI CATIONS This specification was technically approved by th e Global Silicon Wafer Committee an…

SEMI M10-1296 © SEMI 1987, 19963

scratch — (macroscratch, microscratch): Long, narrow,

shallow groove or cut below the established plane of

the surface, seen either before or after etching. The ratio

of the length of the figure to the width of the figure

must be greater than 5:1 in order to be defined as a

scratch.

Macroscratches are visible to the unaided eye under

high intensity illumination.

Microscratches are not visible to the unaided eye

under high intensity illumination.

slip — (dislocation pit, preferential etch pits, stress

effect) (see also pit): Process of plastic deformation in

which one part of a crystal undergoes a shear

displacement relative to another in a fashion which

preserves the crystallinity of the material. Slip is

evidenced by a pattern of one or more straight lines of

10 or more dislocation etch pits per millimeter which

do not necessarily touch each other.

striations — Striations appear in Czochralski grown

crystals regardless of their resistivity.

tweezer mark — Any mark on the wafer caused by

handling with tweezers.

twin — A body of crystal within the wafer in which the

lattice is of two parts, related to each other in

orientation as mirror images, across a coherent planar

interface known as the twinning plane or twin

boundary.

NOTICE: These standards do not purport to address

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responsibility of the user of these standards to establish

appropriate safety and health practices and determine

the applicability of regulatory limitations prior to use.

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suitability of the standards set forth herein for any

particular application. The determination of the

suitability of the standard is solely the responsibility of

the user. Users are cautioned to refer to manufacturer’s

instructions, product labels, product data sheets, and

other relevant literature respecting any materials

mentioned herein. These standards are subject to

change without notice.

The user’s attention is called to the possibility that

compliance with this standard may require use of

copyrighted material or of an invention covered by

patent rights. By publication of this standard, SEMI

takes no position respecting the validity of any patent

rights or copyrights asserted in connection with any

item mentioned in this standard. Users of this standard

are expressly advised that determination of any such

patent rights or copyrights, and the risk of infringement

of such rights, are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

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consent of SEMI.

SEMI M11-0704 © SEMI 1988, 2004 1

SEMI M11-0704

SPECIFICATIONS FOR SILICON EPITAXIAL WAFERS FOR

INTEGRATED CIRCUIT (IC) APPLICATIONS

This specification was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the North American Silicon Wafer Committee. Current edition approved by the North

American Regional Standards Committee on April 22, 2004. Initially available at www.semi.org June 2004;

to be published July 2004. Originally published in 1988; previously published November 2003.

1 Purpose

1.1 This specification defines and provides examples

of silicon epitaxial wafer requirements for integrated

circuit device manufacture. It is restricted to wafers of

diameter 100 mm or greater with epitaxial layer

thickness less than or equal to 25 µm. By defining

inspection procedures and acceptance criteria, both

suppliers and consumers may uniformly define product

characteristics and quality requirements.

2 Scope

2.1 This specification covers characteristics of both the

substrate (as specified in SEMI M1) and the epitaxial

layer, in-cluding handling and packaging. The primary

standard-ized properties set forth in this specification

relate to physical, electrical, and surface defect

parameters.

2.2 The primary standard-ized properties set forth in

this specification relate to physical, electrical, and

surface defect parameters.

2.3 A complete purchase specification requires that

additional physical properties be specified along with

suitable test methods for their measurements. SEMI

M18 may be used for this purpose.

2.4 These specifications are specifically directed to

silicon homoepitaxial deposits on homogeneous silicon

substrates only, for which more stringent uniformity

and surface defect criteria are required than specified in

SEMI M2.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory limitations prior to use.

3 Referenced Standards

3.1 SEMI Standards

SEMI M1 — Specifications for Polished Mono-

crystalline Silicon Wafers

SEMI M2 — Specification for Silicon Epitaxial Wafers

for Discrete Device Applications

SEMI M18 — Format for Silicon Wafer Specification

Form for Order Entry

SEMI M43 — Guide for Reporting Wafer

Nanotopography

SEMI M44 — Guide for Conversion Factors for

Interstitial Oxygen in Silicon

SEMI M53 — Practice for Calibrating Scanning

Surface Inspection Systems using Certified Depositions

of Monodisperse Polystyrene Latex Spheres on

Unpatterned Semiconductor Wafer Surfaces

SEMI MF95 — Test Method for Thickness of Epitaxial

Layers of Silicon on Substrates of the Same Type by

Infrared Reflectance

SEMI MF110 — Test Method for Thickness of

Epitaxial or Diffused Layers in Silicon by the Angle

Lapping and Staining Technique

SEMI MF154 — Guide for Identification of Structures

and Contaminants Seen on Specular Silicon Surfaces

SEMI MF374 — Test Method for Sheet Resistance of

Silicon Epitaxial Layers Using an Inline Four-Point

Probe with the Single Configuration

SEMI MF398 — Test Method for Majority Carrier

Con-centration in Semiconductors by Measurement of

Wavelength of the Plasma Resonance Minimum

SEMI MF523 — Practice for Unaided Visual

Inspection of Polished Silicon Slices

SEMI MF525 — Measuring Resistivity of Silicon

Wafers Using a Spreading Resistance Probe

SEMI MF672 — Test Method for Measuring

Resistivity Profiles Perpendicular to the Surface of a

Silicon Wafer Using a Spreading Resistance Probe

SEMI MF723 — Practice for Conversion between

Resistivity and Dopant Density for Boron-Doped and

Phosphorus-Doped Silicon

SEMI MF951 — Test Method for Determination of

Radial Interstitial Oxygen Concentration Variation in

Silicon

SEMI M11-0704 © SEMI 1988, 2004 2

SEMI MF1188 — Test Method for Interstitial Atomic

Oxygen Content of Silicon by Infrared Absorption With

Short Baseline

SEMI MF1239 — Test Methods for Oxygen

Precipitation Characterization of Silicon Wafers by

Measurement of Interstitial Oxygen Reduction

SEMI MF1241 — Terminology of Silicon Technology

SEMI MF1366 — Test Method for Measuring Oxygen

Concentration in Heavily Doped Silicon Substrates by

Secondary Ion Mass Spectrometry

SEMI MF1392 — Test Method for Determining Net

Carrier Density Profiles in Silicon Wafers by

Capacitance-Voltage Measurements with a Mercury

Probe

SEMI MF1393 — Test Method for Determining Net

Carrier Density in Silicon Wafers by Miller Feedback

Profiler Measurements with a Mercury Probe

SEMI MF1726 — Guide for Analysis of

Crystallographic Perfection of Silicon Wafers

SEMI MF1727 — Practice for Detection of Oxidation

Induced Defects in Polished Silicon Wafers

3.2 Other Standards

ANSI/ASQC Z1.4 — Sampling Procedures and Tables

for Inspection by Attributes

ISO 14644-1 — Cleanrooms and associated controlled

environments — Part 1: Classification of airborne

particulates

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Terminology

4.1 Many terms relating to silicon technology are

defined in SEMI MF1241.

4.2 Descriptions of other epitaxial wafer defects

covered in Table 1 are given in SEMI MF154.

4.3 Definitions of selected epi wafer defects, extended

to consider automatic surface inspection are given

below.

4.3.1 mound (epi) — a rounded protrusion on a

semiconductor wafer surface, which may have one or

more partially developed facets (see Figure 1).

1 American Society for Quality Control, 611 East Wisconsin Avenue,

Milwaukee, WI 53202. Website: www.asqc.org.

2 ISO Central Secretariat, C. P. 56, CH-1211 Genève 20,

Switzerland; Website: www.iso.ch; available in the U.S. from

American National Standards Institute, 11 West 42nd Street, 13th

Floor, New York, NY 10036 Website: www.ansi.org.

NOTE 1: Scattering event size reported by SSIS will differ

from the physical size of the object. The figure captions in

the examples highlight this fact. No useful method exists at

the present time to quantify this relationship (see Section

7.3.3.3)

4.3.1.1 Discussion — Related characteristics include

the following:

• Device characteristics that may be affected —

critical feature dimensions, lithographic equipment

focus, gate oxide integrity.

• Detection characteristics used for characterization

— mound height, diameter at 50% height.

• Discrimination characteristics used for

characterization — positive height: 10–100 nm, or

approximately 20% of the epi layer thickness;

diameter: 0.1–6 µm; circular symmetry.

• Specification characteristics used for wafer

qualification — number per wafer, mound height,

height to diameter.

4.3.2 epi stacking fault — a two dimensional effect that

results from a deviation from the normal stacking

sequence of atoms in a crystal. [SEMI MF154, SEMI

MF1727]

NOTE 2: Discrimination and specification characteristics are

given in this section to facilitate equipment development (see

Section 7.3.3.3) and are not intended for use in commercial

wafer specifications.

4.3.2.1 Discussion — Epi stacking faults are typically

linked together into squares in the case of {100}

oriented wafers, and triangles in the case of {111}

oriented wafers. Most stacking faults are nucleated at

the epi layer substrate boundary, though some have

been observed being nucleated further into the epi

growth process. Faults are aligned along specific

crystallographic directions. For {100} wafer the sides

of the faults are aligned along <110> directions. The

length of a side is typically proportional to the epi layer

thickness and related to the crystallographic orientation.

In order to minimize the strain around a stacking fault

contaminants may diffuse to these defects. Some

stacking faults may have an effect on the local growth

rate giving the stacking fault a three dimension aspect.

This three dimensional aspect changes their light

scattering cross section when observed by an SSIS (see

Figures 3 through 7). Still more complicated are

overlapping stacking faults which scatter even more

than a single stacking fault of the same size (see figure

4). Other types of defects may be composites of

stacking faults and polysilicon growth which can also

appear larger than a single stacking fault of the same

lateral dimensions (see Figures 5 and 6). Related

characteristics include the following: