semi合集-English.pdf - 第5432页
SEMI M59-0305 © SEMI 2005 13 6.1.4.1 Discussion — Note that th e y -direction associated with the edge profile template in SEMI M1 is in the vertical direction through the wafer a nd that this dimension is positive away …
SEMI M59-0305 © SEMI 2005 12
5.103 surface texture — the topographic deviations of a real surface from a reference surface.
5.103.1 Discussion — Surface texture includes roughness, waviness, and lay.
5.104 swirl — helical or concentric features that are visible to the unaided eye after preferential etch, and appear to
be discontinuous under 100× magnification.
5.105 terracing — a network of contours that are associated with pyramid-like defects on epitaxially deposited
surfaces and are related to the orientation of the surface.
5.106 thermal emf — the net emf set up in a thermocouple under conditions of zero current. Also known as
Seebeck emf.
5.107 thickness, of a semiconductor wafer — the distance through the wafer between corresponding points on the
front and back surfaces.
5.108 thickness, of an epitaxial layer — the distance from the surface of a wafer to the layer-substrate interface.
5.109 tolerance — the allowable range of a specification parameter on either side of the nominal or target value.
5.110 total indicator reading, TIR — the smallest perpendicular distance between two planes, both parallel with the
reference plane, that encloses all points on the front surface of a wafer within the FQA, the site, or the subsite,
depending on which is specified.
5.111 total thickness variation, TTV — the difference between the maximum and minimum values of the thickness
of a wafer.
5.111.1 Discussion — Initially, the TTV was determined by measurement at a small number of points, generally
five or nine, but modern measurement equipment samples the wafer at relatively small intervals over its entire
extent.
5.112 twin boundary — a coherent planar interface that separates two parts of a crystal lattice that are related to
each other in orientation as mirror images.
5.113 warp, of a semiconductor wafer — the difference between the maximum and minimum distances of the
median surface of a free, unclamped wafer from a reference plane.
5.114 waviness — the more widely spaced component of surface texture.
5.114.1 Discussion — Waviness may be caused by such factors as machine or work piece deflections, vibration, and
chatter. Roughness may be considered as superimposed on a wavy surface
6 Symbols
6.1 English Alphabetical Symbols
6.1.1 r — radial dimension of wafer coordinate system with origin at the wafer center.
6.1.1.1 Discussion — Note that the radial dimension associated with the edge profile template in SEMI M1 is called
x and that this dimension is positive away from the actual edge of the wafer.
6.1.2 t — wafer thickness.
6.1.2.1 Discussion — The wafer thickness is sometimes indicated with a capital T, but this usage is to be
discouraged because T also stands for temperature.
6.1.3 x — direction of the wafer coordinate system along the diameter perpendicular to the bisector of the primary
fiducial with origin at the center and positive direction to the right when the top surface is up and the primary
fiducial is toward the operator.
NOTE 2: See also ¶6.1.1.1.
6.1.4 y — direction of the wafer coordinate system along the diameter that is the bisector of the primary fiducial
with origin at the center and positive direction to the top (away from the fiducial) when the top surface is up and the
primary fiducial is toward the operator.
SEMI M59-0305 © SEMI 2005 13
6.1.4.1 Discussion — Note that the y-direction associated with the edge profile template in SEMI M1 is in the
vertical direction through the wafer and that this dimension is positive away from the actual surface of the wafer.
6.1.5 z — direction of the wafer coordinate system through the bulk of wafer with the positive direction upwards
when the top surface is up.
NOTE 3: See also ¶6.1.4.1.
6.2 Greek letters
6.2.1 — delta, difference.
6.2.2
— angular direction in a counter clockwise direction from the diameter perpendicular to the bisector of the
primary fiducial in the wafer coordinate system.
6.2.3 — micro, one millionth, usually associated with meters (m) or seconds (s).
6.2.4
— carrier mobility as of an electron or hole in a semiconductor.
6.2.5
— resistivity.
6.2.6
— conductivity.
6.2.7 — ohm, the unit of resistance, combined with a linear dimension, usually centimeter, to be the unit of
resistivity.
6.3 Mathematical symbol
6.3.1 — multiplication sign, also sometimes indicated by a center dot (·) especially when separating various units
in a group of units such as ·cm.
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SEMI M60-0305 © SEMI 2005 1
SEMI M60-0305
TEST METHOD FOR TIME DEPENDENT DIELECTRIC BREAKDOWN
CHARACTERISTICS OF SiO2 FILMS FOR Si WAFER EVALUATION
This test method was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional
Standards Committee on January 11, 2005. Initially available at www.semi.org January 2005; to be
published March 2005.
1 Purpose
1.1 The technique outlined in this test method is for the purpose of standardizing silicon wafer characterization by
GOI (Gate Oxide Integrity). For more detailed discussion of the general characterizing methods for this test, the
reader is referred to §3. TZDB technique as SEMI M51 is advantageous to estimate failure rate by intrinsic
breakdown as the C mode and an accidental breakdown as the B mode. However, this test method has a higher
sensitivity for detecting the accidental breakdown mode than TZDB.
2 Scope
2.1 This test method is for the purpose of the characterization method of silicon wafer by GOI. This
characterization method is outlined below
2.1.1 MOS (Metal Oxide Semiconductor) — capacitor fabrication — A gate oxide film is thermally grown on a
silicon wafer surface. Then, poly-Si electrodes are formed on the gate oxide film. Other metals, other than poly-
silicon electrode materials, can be used, however, it shall be desirable to use an electrode that has been confirmed to
have sufficiently good characteristics for application as a gate electrode as described below.
2.1.2 Electrical Characterization Evaluation — The TDDB (Time Dependent Dielectric Breakdown) characteristics
of the MOS capacitors are measured. The presence of COPs (Crystal Originated Particles) at the surface of the
polished Si substrates influences the TDDB characteristics of the gate oxide. That is, the silicon wafer is evaluated
in terms of the TDDB characteristics of the gate oxide. The test method outlined in this test method is for the
purpose of standardizing the procedure of MOS fabrication, measurement, analyses, and the report of the GOI data
to interested parties. This test method is based on the results of round robin among the silicon wafer manufacturers.
In general, GOI strongly depends on crystal defects, contaminations and particles on/near wafer surface. GOI also
depends on the fabrication environment. The cleanliness of the process environment in which the MOS capacitors
are fabricated shall be evaluated to be acceptable (see ¶5.3).
2.2 The target of this test method is to characterize silicon wafers, that is, evaluate COPs near the silicon wafer
surface. The proper gate oxide thickness of the MOS samples is 20–25 nm. A discussion on gate oxide thickness is
given in a later section. Oxygen precipitates are also one of the gate oxide defect origins, however, this is beyond
the scope of this test method because the as-received wafers contain only a small amount of oxygen precipitates.
Near-surface quality can be evaluated in this test. In this case, it is assumed that an oxide film thickness of
approximately 10 nm is used. It is more difficult to categorize the accidental and intrinsic breakdowns in TZDB, as
the gate oxide thickness becomes thinner. Therefore mode classification in TDDB is more effective.
2.3 For detailed discussion on sample structures used in this test method, the reader shall refer to EIA/JEDEC
Standard 35-1. In general, the most likely sample structures are a simple planar MOS (Metal Oxide Semiconductor)
capacitor structure, various isolation structures (for example, LOCOS (LOCal Oxidation of Silicon), STI (Shallow
Trench Isolation)), and FET (Field-Effect Transistor) structures. For the purpose of silicon wafer characterization,
the simple planar MOS capacitor structure is the most desirable. In the case of the various isolation and FET
structures, the silicon wafer receives thermal treatments several times in the complicated sample fabrication process.
Therefore, in this case it is questionable whether the characteristics of the starting Si wafer are reflected in this test
measurement results.
2.4 In this evaluation method, a constant current stress is applied to the gate oxide and time to breakdown is
measured. The amount of charge injected until dielectric breakdown (Q
bd
) is also calculated. (Constant-current
TDDB: detail of measurement condition is described in a later section). The dielectric breakdown by the COPs and
other defects can be evaluated from the accumulated failure distribution of Q
bd
. In addition, a constant-voltage